CY7C68013-56LFC Cypress Semiconductor Corp, CY7C68013-56LFC Datasheet - Page 48

• Manufacturer Part Number: CY7C68013-56LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C68013-56LFC

• Cpu Family: FX2LP
• Device Core: 8051
• Device Core Size: 8b
• Frequency (max): 48MHz
• Interface Type: USB
• Program Memory Type: ROMLess
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 24
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Instruction Set Architecture: CISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 56
• Package Type: QFN EP
• Lead Free Status / Rohs Status: Not Compliant

Document History Page
Document #: 38-08012 Rev. *F
Document Title: CY7C68013 EZ-USB FX2™ USB Microcontroller High-speed USB Peripheral Controller
Document Number: 38-08012
REV.
*C
*D
*A
*B
*E
*F
**
ECN NO. Issue Date
120776
288810
317674
352234
111753
111802
115480
See ECN
See ECN
See ECN
11/15/01
02/20/02
06/26/02
01/06/03
Change
Orig. of
MON
MON
MON
DSG
KKU
KKU
KKU
Changed from Spec number: 38-00929 to 38-08012
Updated functional changes between revision D part and revision E part
Changed timing data from simulation data to revision E characterization data
Added new 56-pin Quad Flatpack No Lead package and pinout
Revised pin description table to reflect new package
Corrected Figure 9-8 by moving tsfd parameter location
Corrected labels on Dplus and Dminus in Table 4-1
Removed Preliminary from spec title
Added bus powered references and PCB layout recommendations and QFN
package design notes
Updated QFN package drawing 51-85144 to current revision
Added lead-free packages
Added timing sequence diagrams for slave FIFO read and write
Changed PKTEND to FLAGS output propagation delay (asynchronous
interface) in Table 9-13from a max value of 70 ns to 115 ns
Changed FIFOADR[2:0] Hold Time (t
follows:
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode).
Added information on the AUTOPTR1/AUTOPTR2 address timing with
regards to data memory read/write timing diagram.
Added information “This part is not recommended for new designs. Use EZ-
USB FX2LP instead of EZ-USB FX2 for new designs”
SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns
SLWR to FIFOADR[2:0] Hold Time: 70 ns
Description of Change
FAH )
for Asynchronous FIFO Interface as
CY7C68013
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