UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 233

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(2) Analog input channel specification register 0 (ADS0)
(3) A/D conversion result register 0 (ADCR0)
Address: FF81H After reset: 00H R/W
Symbol
ADS0
Caution
This register specifies the analog voltage input port for A/D conversion.
ADS0 is set by an 8-bit memory manipulation instruction.
RESET input clears ADS0 to 00H.
This is a 16-bit register that stores the A/D conversion results. The lower 6 bits are fixed to 0. Each time A/D
conversion ends, the conversion result is loaded from the successive approximation register (SAR) and held by
this register. The most significant bit (MSB) is stored in ADCR0 first. The higher 8 bits of the conversion results
are stored in FF17H. The lower 2 bits of the conversion results are stored in FF16H.
ADCR0 is read by a 16-bit memory manipulation instruction.
RESET input sets ADCR0 to 0000H.
ADCR0
Symbol
Caution
Figure 13-5. Format of Analog Input Channel Specification Register 0 (ADS0)
Address: FF16H, FF17H After reset: 0000H R
When A/D converter mode register 0 (ADM0) and analog input channel specification register
0 (ADS0) are written, the contents of ADCR0 may become undefined. Read the conversion
result following conversion completion before writing to ADM0 and ADS0. Using a timing other
than the above may cause an incorrect conversion result to be read.
ADS02
7
0
0
0
0
0
1
1
1
1
Figure 13-6. Format of A/D Conversion Result Register 0 (ADCR0)
Be sure to clear bits 3 to 7 to “0”.
ADS01
6
0
0
0
1
1
0
0
1
1
FF17H
CHAPTER 13 A/D CONVERTER
ADS00
5
0
0
1
0
1
0
1
0
1
User’s Manual U14260EJ4V0UD
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
4
0
Analog input channel specification
3
0
0
ADS02
0
FF16H
2
0
ADS01
0
1
0
0
ADS00
0
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