UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 407

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
Address: FF48H After reset: 00H R/W
Symbol
EGP
Address: FF49H After reset: 00H R/W
Symbol
EGN
These registers specify the valid edge for INTP0 to INTP3.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears EGP and EGN to 00H.
Table 19-3 shows the ports corresponding to EGPn and EGNn.
Remark n = 0 to 3
Caution When the function is switched from external interrupt request to port, edge detection
Figure 19-5. Format of External Interrupt Rising Edge Enable Register (EGP) and
EGPn
7
0
7
0
0
0
1
1
Detection Enable Register
EGP0
EGP1
EGP2
EGP3
may be performed. Therefore, clear EGPn and EGNn to 0 before switching to the port
mode.
Table 19-3. Ports Corresponding to EGPn and EGNn
EGNn
External Interrupt Falling Edge Enable Register (EGN)
6
0
6
0
0
1
0
1
CHAPTER 19 INTERRUPT FUNCTIONS
EGN0
EGN1
EGN2
EGN3
Edge detection disabled
Falling edge
Rising edge
Both rising and falling edges
5
0
5
0
User’s Manual U14260EJ4V0UD
P00
P01
P02
P03
Edge Detection Port
INTPn pin valid edge selection (n = 0 to 3)
4
0
4
0
EGP3
EGN3
3
3
INTP0
INTP1
INTP2
INTP3
Interrupt Request Signal
EGP2
EGN2
2
2
EGN1
EGP1
1
1
EGP0
EGN0
0
0
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