UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 286

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

284
Figure 15-10. Minimum Permissible Data Frame Length and Maximum Permissible Data Frame Length
Data frame length
of UART2
Minimum permissible
data frame length
Maximum permissible
data frame length
• Permissible baud rate range for reception
As shown in the timing chart in Figure 15-10, the latch timing of the receive data is determined by the
counter set by using baud rate generator control register 2 (BRGC2) after the start bit has been detected.
If the last data (stop bit) is received within this latch timing, the data can be correctly received.
This latch timing has a margin of two clocks.
Take reception of 11-bit data as an example.
Therefore, the maximum receivable baud rate of the transmission destination is as follows.
1 bit data length of UART2: FL = (Brate)
Minimum permissible data frame length: FLmin = 11
BRmax = (FLmin/11)
CHAPTER 15 SERIAL INTERFACE UART2
–1
=
21k + 2
Start
Start
Start
22k
User’s Manual U14260EJ4V0UD
D0
Brate
D0
FL
D0
–1
D1
D1
D1
1 data frame (11
=
21k + 2
FLmin
2k
FLmax
FL –
k – 2
FL
2k
FL)
D7
D7
D7
FL
P
P
P
Stop
Stop
Stop