UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 259

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Baud Rate
600
1200
2400
4800
9600
19200
31250
38400
76800
115200
(bps)
• Error tolerance range for baud rate
Caution
Remark f
Baud rate error tolerance (when k = 0) =
Remark T: 5-bit counter’s source clock cycle
[1/(16 + k)].
The error for the baud rate depends on the number of bits per frame and the 5-bit counter’s division ratio
Figure 14-7 shows an example of the baud rate error tolerance range.
High-speed limit timing
Low-speed limit timing
Basic timing
BRGC0
f
X
7BH
6BH
5BH
4BH
3BH
31H
2BH
1BH
12H
X
The above error tolerance value is the value calculated based on the ideal sample point. In
the actual design, allow margins that include errors of timing for detecting a start bit.
–
: Main system clock oscillation frequency
= 8.3886 MHz
Table 14-3. Relationship Between Main System Clock and Baud Rate Error
Figure 14-7. Error Tolerance (When k = 0), Including Sampling Errors
ERR (%)
1.10
1.10
1.10
1.10
1.10
–1.3
1.10
1.10
1.10
–
BRGC0
CHAPTER 14 SERIAL INTERFACE UART0
7AH
6AH
5AH
4AH
3AH
2AH
1AH
30H
11H
f
X
–
= 8.000 MHz
START
START
START
ERR (%)
User’s Manual U14260EJ4V0UD
30.45T
0.16
0.16
0.16
0.16
0.16
0.16
0.16
2.12
33.55T
–
0
32T
320
15.5
D0
D0
D0
BRGC0
f
2DH
78H
68H
58H
48H
38H
28H
18H
10H
X
100 = 4.8438 (%)
60.9T
–
= 7.3728 MHz
67.1T
64T
ERR (%)
256T
1.70
D7
–
0
0
0
0
0
0
0
0
D7
BRGC0
70H
60H
50H
40H
30H
24H
20H
10H
f
X
–
–
288T
D7
= 5.000 MHz
P
sampling
301.95T
304.5T
304T
Ideal
point
ERR (%)
P
15.5T
1.73
1.73
1.73
1.73
1.73
1.73
1.73
STOP
–
0
–
320T
P
15.5T
STOP
335.5T
BRGC0
336T
f
7BH
6BH
5BH
4BH
3BH
2BH
1BH
21H
X
–
–
STOP
= 4.1943 MHz
Sampling error
0.5T
352T
ERR (%)
1.14
1.14
1.14
1.14
1.14
1.14
–1.3
1.14
–
–
257