UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 359

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

18.5.11 Arbitration
to 1
differs. This kind of operation is called arbitration.
is set (1) via the timing by which the arbitration loss occurred, and the SCL0 and SDA0 lines are both set to high
impedance, which releases the bus.
a stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
Transfer lines
Master 1
Master 2
When several master devices simultaneously output a start condition (when STT0 is set to 1 before STD0 is set
When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in IIC status register 0 (IICS0)
The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when
For details of interrupt request timing, see 18.5.16 Timing of I
Note STD0: Bit 1 of IIC status register 0 (IICS0)
Note
), communication among the master devices is performed as the number of clocks are adjusted until the data
STT0: Bit 1 of IIC control register 0 (IICC0)
SDA0
SDA0
SDA0
SCL0
SCL0
SCL0
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
Figure 18-17. Arbitration Timing Example
User’s Manual U14260EJ4V0UD
2
C interrupt request (INTIIC0) occurrence.
Master 1 loses arbitration
Hi-Z
Hi-Z
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