UPD78F0078GK-9ET-A Renesas Electronics America, UPD78F0078GK-9ET-A Datasheet - Page 348

• Manufacturer Part Number: UPD78F0078GK-9ET-A
• Manufacturer: Renesas Electronics America

Specifications of UPD78F0078GK-9ET-A

• Lead Free Status / Rohs Status: Supplier Unconfirmed

(3) IIC transfer clock select register 0 (IICCL0)
Address: FFAAH After reset: 00H
346
Symbol
IICCL0
This register is used to set the transfer clock for the I
IICCL0 is set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears IICCL0 to 00H.
Note Bits 4 and 5 are read-only bits.
Remark IICE0: Bit 7 of IIC control register 0 (IICC0)
Condition for clearing (CLD0 = 0)
• When the SCL0 line is at low level
• When IICE0 = 0 (operation stop)
• When RESET is input
Condition for clearing (DAD0 = 0)
• When the SDA0 line is at low level
• When IICE0 = 0 (operation stop)
• When RESET is input
Condition for clearing (SMC0 = 0)
• Cleared by instruction
• When RESET is input
SMC0
CLD0
DAD0
7
0
0
1
0
1
0
1
Figure 18-7. Format of IIC Transfer Clock Select Register 0 (IICCL0) (1/2)
CHAPTER 18 SERIAL INTERFACE IIC0 ( PD780078Y SUBSERIES ONLY)
SCL0 line was detected at low level.
SCL0 line was detected at high level.
SDA0 line was detected at low level.
SDA0 line was detected at high level.
Operation in standard mode
Operation in high-speed mode
6
0
R/W
CLD0
5
Note
Detection of SDA0 line level (valid only when IICE0 = 1)
Detection of SCL0 line level (valid only when IICE0 = 1)
User’s Manual U14260EJ4V0UD
DAD0
4
Operation mode switching
2
SMC0
C bus.
3
Condition for setting (CLD0 = 1)
• When the SCL0 line is at high level
Condition for setting (DAD0 = 1)
• When the SDA0 line is at high level
Condition for setting (SMC0 = 1)
• Set by instruction
DFC0
2
1
0
CL00
0