A43L0616BV-7F AMIC, A43L0616BV-7F Datasheet

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... Add 54B Pb-Free CSP package type 1.3 art numbering scheme Add p (February, 2008, Version 1.3) 512K X 16 Bit X 2 Banks Synchronous DRAM A43L0616B Issue Date Remark May 12, 2003 Preliminary February 27, 2006 April 6, 2006 Final July 19, 2006 July 5, 2007 February 15, 2008 AMIC Technology, Corp. ...

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... General Description The A43L0616B is 16,777,216 bits synchronous high data rate Dynamic RAM organized 524,288 words by 16 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on ...

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... Pin Configuration (continued) TSOP (II (February, 2008, Version 1. A43L0616BV A43L0616B AMIC Technology, Corp. ...

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... ADD LRAS LRAS LCBR CLK (February, 2008, Version 1.3) Data Input Register 512K X 16 512K X 16 Column Decoder Latency & Burst Length Programming Register LCAS LWE Timing Register CKE CS RAS CAS 3 LDQM LWCBR L(U)DQM WE AMIC Technology, Corp. A43L0616B LWE LDQM DQi ...

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... Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +3.3V ± 0.3V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. 4 A43L0616B Description AMIC Technology, Corp. ...

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... DQ0 to DQ15 A Symbol Min Typ 3.0 3.3 V 2 Min Typ 2 2 CAS 0ºC to +70ºC or -40ºC to +85ºC) Max Unit 3.6 V VDD+0 0 0.4 V μ μ See Figure 1 AMIC Technology, Corp. A43L0616B Max Unit Note Note -2mA 2mA OL Note 2 Note 3 ...

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... Page Burst OL All bank Activated (min) CCD CCD ≥ (min CKE ≤ 0.2V 6 Value 0.1 + 0.01 DC1 0.1 + 0.01 DC2 CAS Spec. Latency 60 700 = 15ns 6 = ∞ 0 15ns 30 = ∞ 800 (min). CC (min). CC AMIC Technology, Corp. A43L0616B Unit μ F μ F Unit Notes ...

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... DC Output Load Circuit (February, 2008, Version 1.3) Value 2.4V/0. 1.4V tr/tf = 1ns/1ns 1.4V See Fig.2 3.3V V (DC) = 2.4V -2mA OH OH 1200Ω V (DC) = 0.4V 2mA OL OL 30pF 7 A43L0616B V =1.4V TT 50Ω Z =50Ω OUTPUT O 30pF (Fig Output Load Circuit AMIC Technology, Corp. ...

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... Version 1.3) -6 CAS Latency Min Max 3 6 1000 5 6.0 2.0 2.0 - 2.0 2.0 - 2.0 2 A43L0616B -7 Unit Min Max 7 1000 6 6.5 2 2.0 2 2.0 2 *All AC parameters are measured from half to half. AMIC Technology, Corp. Note 1 1 ...

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... Minimum delay is required to complete write. 3. All parts allow every cycle column address change case of row precharge interrupt, auto precharge and read burst stop. (February, 2008, Version 1.3) CAS Version Latency - 100 A43L0616B Unit Note - μ AMIC Technology, Corp. ...

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... Hi-Z state after 2 CLK cycles. (Read DQM latency is 2) (February, 2008, Version 1.3) CKEn-1 CKEn CS RAS CAS Exit Exit Valid Don’t Care Logic High Logic Low) 10 A43L0616B DQM BA A10/ A9~ CODE Row Addr. L Column Addr Column Addr AMIC Technology, Corp. Notes 1 4 ...

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... Version 1. CAS Latency CAS Latency Burst Type Latency Reserved Reserved Reserved Reserved Reserved Burst Length Burst Length Type BT=0 Sequential Interleave Reserved Reserved Reserved 256(Full) AMIC Technology, Corp. A43L0616B A1 A0 BT=1 Reserved Reserved 4 8 Reserved Reserved Reserved Reserved (Note 3) ...

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... Burst Sequence (Burst Length = 4) Initial address Burst Sequence (Burst Length = 8) Initial address (February, 2008, Version 1.3) Sequential Sequential A43L0616B Interleave Interleave AMIC Technology, Corp ...

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... SDRAM operation. Refer to table for specific codes for various burst length, addressing modes and CAS latencies. high disables the 13 A43L0616B WE and , and all the CAS CAS and BA in the same WE going low is the data written in the AMIC Technology, Corp (The cycle as ...

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... The number of clock cycles required between different bank activation must be calculated similar to t minimum time required for the bank to be active to initiate sensing and restoring the complete row of dynamic cells is determined by t (min) specification before a precharge RAS command to that active bank can be asserted ...

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... CKE and burst 2048 auto refresh cycles immediately after exiting self refresh. 15 A43L0616B (min)”. The minimum number RAS , and CKE with high on CAS ” before the SDRAM reaches idle RC AMIC Technology, Corp. ” with RC ...

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... DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”. 2. DQM masks both data-in and data-out. (February, 2008, Version 1.3) 2) Clock Suspended During Read (BL= Read Mask (BL=4) RD Hi-Z Hi Hi-Z Hi Masked by CKE Suspended Dout Masked by CKE Hi Hi DQM to Data-out Mask = AMIC Technology, Corp. A43L0616B Q3 ...

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... Version 1.3) Note 1 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 DQ(CL2) DQ(CL3) access; read, write and block write. CAS 17 3) Write interrupted by Read (BL = CCD Note2 A B DA0 QB0 QB1 DA0 QB0 t CDL Note3 AMIC Technology, Corp. A43L0616B QB1 ...

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... Note : 1. To prevent bus contention, there should be at least one gap between data in and data out prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. (February, 2008, Version Note Hi Hi Note 2 18 A43L0616B AMIC Technology, Corp. ...

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... The new read/write command of other active bank can be issued from this point. At burst read/write with auto precharge, (February, 2008, Version 1.3) Note 2 PRE Note Masked by DQM PRE RDL PRE Note 1 Auto Precharge Starts Note 1 Auto Precharge Starts interrupt of the same/another bank is illegal. CAS 19 A43L0616B from this point. RP AMIC Technology, Corp. ...

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... MRS can be issued only at all bank precharge state. (February, 2008, Version 1.3) 2) Write Burst Stop (BL=8) PRE D2 D3 Note 1 t RDL 4) Read Burst Stop (BL=4) PRE Note DQ(CL2 DQ(CL3) MRS ACT t 1CLK RP 20 A43L0616B CLK CMD WR STOP (note 2) BDL CLK CMD RD STOP AMIC Technology, Corp. Note ...

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... RC Before/After self refresh mode, burst auto refresh cycle (2K cycles ) is recommended. (February, 2008, Version 1.3) 2) Power Down (=Precharge Power Down) Exit t SS Internal CLK CKE t SS Note 2 CLK NOP ACT CMD Note AMIC Technology, Corp. A43L0616B ...

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... During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, 22 A43L0616B interrupt can not be issued. CAS AMIC Technology, Corp. ...

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... Power On Sequence & Auto Refresh CLOCK CKE High level is necessary RAS CAS ADDR BA A10/AP WE DQM High level is necessary High-Z DQ Precharge Auto Refresh (All Banks) (February, 2008, Version 1. Auto Refresh KEY KEY KEY Mode Regiser Set AMIC Technology, Corp. A43L0616B Row Active (A-Bank) : Don't care ...

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... SH CAS ADDR *Note 2,3 *Note *Note 3 A10/ DQM t RAC DQ Read Row Active (February, 2008, Version 1. High t RAS CCD *Note 2,3 *Note 2 *Note 3 *Note SAC SLZ SHZ Read Write *Note 4 *Note *Note Row Active Precharge AMIC Technology, Corp. A43L0616B Don't care ...

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... Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. BA Precharge 0 Bank A 1 Bank B X Both Bank 25 A43L0616B AMIC Technology, Corp. ...

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... Qa0 Qa1 Qa2 Qa3 *Note SHZ SAC Precharge Row Active (A-Bank) (A-Bank) from the clock. SHZ *(t + CAS latency- RCD SAC 26 A43L0616B Cb0 Db0 Db1 Db2 Db3 t RDL Db0 Db1 Db2 Db3 t RDL Write Precharge (A-Bank) (A-Bank) AMIC Technology, Corp Don't care ...

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... Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Dc0 Write Read (A-Bank) (A-Bank) before Row precharge, will be written. RDL 27 A43L0616B *Note 2 Cd0 t RDL t CDL *Note3 Dc1 Dd0 Dd1 Dc1 Dd0 Dd1 Write Precharge (A-Bank) (A-Bank) : Don't care AMIC Technology, Corp ...

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... CAc CBd CAe QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 Read Read Read Precharge (A-Bank) (B-Bank) (A-Bank) AMIC Technology, Corp. A43L0616B 18 19 *Note 2 (A-Bank) : Don't care ...

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... To interrupt burst write by Row precharge, both the write and precharge banks must be the same. (February, 2008, Version 1. High RBb CBb RBb DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 t CDL Row Active Write (B-Bank) (B-Bank *Note 2 CAc CBd DBd0 DBd1 t RDL *Note 1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) AMIC Technology, Corp. A43L0616B Don't care ...

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... QAa1 QAa2 QAa3 Precharge (A-Bank) Row Active (B-Bank CBb RAc CAc RAc t CDL *Note 1 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write Read (B-Bank) (A-Bank) Row Active (A-Bank) AMIC Technology, Corp. A43L0616B 18 19 QAc0 QAc1 QAc2 QAc0 QAc1 : Don't care ...

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... High CAa QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Auto Precharge Start Point (A-Bank CBb DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write with Auto Precharge Start Point Auto Precharge (B-Bank) AMIC Technology, Corp. A43L0616B 18 19 (B-Bank) : Don't care ...

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... Qb0 Qb1 Read without Auto Precharge (B-Bank) Auto Precharge Strart Point (A-Bank) *Note 1 after A Bank auto precharge starts Qb3 Qb2 Qb3 Precharge Row Active (B-Bank) (A-Bank) AMIC Technology, Corp. A43L0616B Da0 Da1 Da0 Da1 Write with Auto Precharge (A-Bank) : Don't care ...

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... Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 * Note 1 Auto Precharge Read with Auto Precharge Start Point (A-Bank) (B-Bank) Row Active (B-Bank Qb0 Qb1 Qb2 Qb3 Qb0 Qb1 Db2 Db3 Auto Precharge Start Point (B-Bank) AMIC Technology, Corp. A43L0616B Don't care ...

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... High CAb * Note 1 * Note 2 1 QAa1 QAa2 QAa3 QAa4 QAa0 2 QAa0 QAa1 QAa2 QAa3 QAa4 Read Burst Stop (A-Bank) 34 A43L0616B QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 Precharge (A-Bank) RAS interrupt. AMIC Technology, Corp Don't care ...

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... Burst stop is valid only at every burst length. (February, 2008, Version 1. High CAb * Note 1 t BDL * Note 2 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 Write Burst Stop (A-Bank RDL * Note 3 DAb4 DAb5 Precharge AMIC Technology, Corp. A43L0616B 18 19 (A-Bank) : Don't care ...

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... CAb RAc RBb RAc QAb0 QAb1 QAb0 QAb1 Row Active (A-Bank) Read with Auto Precharge (A-Bank Note 2 CBc CAd DBc0 QAd0 QAd1 DBc0 QAd0 Read (A-Bank) Write with Auto Precharge (B-Bank) AMIC Technology, Corp. A43L0616B 18 19 QAd1 Precharge (A-Bank) : Don't care ...

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... DQM DQ Row Active Read * Note : DQM needed to prevent bus contention. (February, 2008, Version 1. Qa0 Qa1 Qa2 Qa3 t SHZ Clock Read Suspension Note 1 Qb0 Qb1 Dc0 Dc2 t SHZ Write Read DQM DQM Write AMIC Technology, Corp. A43L0616B 18 19 Clock Suspension : Don't care ...

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... CKE should be set high at least “1CLK + t 3. Cannot violate minimum refresh specification. (32ms) (February, 2008, Version 1. Note Precharge Power-down Exit Row Active Active Active Power-down Power-down Exit Entry ” prior to Row active command Qa0 Qa1 Qa2 Read Precharge AMIC Technology, Corp. A43L0616B Don't care ...

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... If the system uses burst refresh. (February, 2008, Version 1. Note 4 * Note 3 Hi-Z Self Refresh Exit 39 A43L0616B min Note 6 * Note 5 * Note 7 Auto Refresh AMIC Technology, Corp Don't care ...

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... Minimum 2 clock cycles should be met before new 3. Please refer to Mode Register Set table. (February, 2008, Version 1.3) Auto Refresh Cycle Auto Refresh WE activation at the same clock cycle with address key will set internal RAS activation. 40 A43L0616B High t RC Hi-Z New Command AMIC Technology, Corp Don't care ...

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... CA,A10/AP Term burst; Begin Read; Latch CA; Determine ILLEGAL L BA A10/AP Term Burst; Precharge timing for Writes ILLEGAL NOP(Continue Burst to End → Precharge NOP(Continue Burst to End → Precharge ILLEGAL H BA CA,A10/AP ILLEGAL L BA CA,A10/AP ILLEGAL X BA RA, PA ILLEGAL ILLEGAL 41 A43L0616B Action Note AMIC Technology, Corp. ...

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... NOP → Row Active after NOP → Row Active after ILLEGAL X BA CA,A10/AP ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP → Idle after NOP → Idle after ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address 42 A43L0616B Action RCD RCD Auto Precharge PA = Precharge All AMIC Technology, Corp. Note ...

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... L X ILLEGAL ILLEGAL ILLEGAL Enter Self Refresh ILLEGAL NOP Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 43 A43L0616B Action RC RC (min) has to be elapse after CKE’s low to RC AMIC Technology, Corp. Note ...

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... MHz 55: 183 MHz 5: 200 MHz Package Type V: TSOP G: CSP Device Version* Mobile Function* I/O Width 16: 16 I/O 32: 32 I/O Device Density 06: 1M 16: 2M 26: 4M 36: 8M 46: 16M 83: 256K Operating Vcc L: 3V~3.6V P: 2.3V~2.7V E: 1.7V~1.95V Device Type A43: AMIC SDRAM AMIC Technology, Corp. ...

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... Ordering Information Part No. Cycle Time (ns) A43L0616BV-6F 6 A43L0616BG-6F 6 A43L0616BV-7F 7 A43L0616BG-7F 7 A43L0616BV-7UF 7 A43L0616BG-7UF 7 Note: -F for Pb-Free for industrial operating temperature range (February, 2008, Version 1.3) Clock Frequency (MHz) Access Time 166 @ 5 100 @ 6 166 @ 5 100 @ 6 143 @ 6 100 @ 6 143 @ 6 100 @ 6 143 @ 6 100 @ 6 143 @ 6 100 @ 6 A43L0616B ...

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... Package Information 54 Balls CSP ( mm) Outline Dimensions (February, 2008, Version 1.3) 8.00 ± 0.10 46 A43L0616B unit: mm 0.40 ± 0.05 AMIC Technology, Corp. ...

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... Detail "A" R0.15 REF. R0.15 REF. θ Detail "A" Dimensions in mm Min Nom Max - - 1. 1.016 1.05 - 0.45 - 0.21 20.955 21.055 11.76 11.96 10.16 10.26 - 0.800 - 0.50 0.60 0° - 5° AMIC Technology, Corp. A43L0616B ...