PALCE16V8Z-25PI

Manufacturer Part NumberPALCE16V8Z-25PI
DescriptionSPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
ManufacturerLattice
PALCE16V8Z-25PI datasheet
 

Specifications of PALCE16V8Z-25PI

Package20PDIPFamily NamePAL®
Maximum Propagation Delay Time25 nsTypical Operating Supply Voltage5 V
Maximum Internal Frequency50 MHzNumber Of Product Terms Per Macro8
Re-programmability SupportYes  
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DISTINCTIVE CHARACTERISTICS
Pin and function compatible with all 20-pin PAL
Electrically erasable CMOS technology provides reconfigurable logic and full testability
High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
Direct plug-in replacement for the PAL16R8 series
Outputs programmable as registered or combinatorial in any combination
Peripheral Component Interconnect (PCI) compliant
Programmable output polarity
Programmable enable/disable control
Preloadable output registers for testability
Automatic register reset on power up
Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
Extensive third-party software and programmer support
Fully tested for 100% programming and functional yields and high reliability
5-ns version utilizes a split leadframe for improved performance
GENERAL DESCRIPTION
The PALCE16V8 is an advanced PAL device built with low-power, high-speed, electrically-
erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The
macrocells provide a universal device architecture. The PALCE16V8 will directly replace the
PAL16R8, with the exception of the PAL16C1.
The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby
current, the PALCE16V8Z allows battery-powered operation for an extended period.
The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to
implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic
can always be reduced to sum-of-products form, taking advantage of the very wide input gates
available in PAL devices. The equations are programmed into the device through floating-gate
cells in the AND logic array that can be erased electrically.
The fixed OR array allows up to eight data product terms per output for logic functions. The
sum of these products feeds the output macrocell. Each macrocell can be programmed as
registered or combinatorial with an active-high or active-low output. The output configuration
is determined by two global bits and one local bit controlling four multiplexers in each
macrocell.
Publication# 16493
Rev: F
Amendment/0
Issue Date: September 2000
PALCE16V8
COM’L:H-5/7/10/15/25, Q-10/15/25 IND:H-10/15/25, Q-20/25
PALCE16V8Z
COM’L:-25
PALCE16V8 and PALCE16V8Z Families
EE CMOS (Zero-Power) 20-Pin Universal
Programmable Array Logic
®
devices
IND:-12/15/25

PALCE16V8Z-25PI Summary of contents

  • Page 1

    ... The PALCE16V8 will directly replace the PAL16R8, with the exception of the PAL16C1. The PALCE16V8Z provides zero standby power and high speed. At 30-µA maximum standby current, the PALCE16V8Z allows battery-powered operation for an extended period. The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and effi ...

  • Page 2

    ... FUNCTIONAL DESCRIPTION The PALCE16V8 is a universal PAL device. The PALCE16V8Z is the zero-power version of the PALCE16V8. It has all the architectural features of the PALCE16V8. In addition, the PALCE16V8Z has zero standby power and an unused product term disable feature for reduced power consumption. It has eight independently configurable macrocells (MC be confi ...

  • Page 3

    ... SL0 SL1 CLK Q X Figure 1. PALCE16V8 Macrocell , a macrocell configured as a dedicated input derives the 7 derives its input from pin 11 (OE) and MC 0 through SL0 0 are the control signals for all four multiplexers PALCE16V8 and PALCE16V8Z Families To Adjacent Macrocell I From Adjacent ...

  • Page 4

    ... The output buffer is disabled. Except x Table 1. Macrocell Configuration Devices Emulated SG0 SG1 PAL16R8, 16R6 16R4 PAL16R6, 16R4 PALCE16V8 and PALCE16V8Z Families . 0 and MC , the feedback signals 0 7 Cell Devices SL0 X Configuration Emulated Device Uses No Registers PAL10H8, 12H6, Combinatorial 0 14H4, 16H2, 10L8, ...

  • Page 5

    ... It can also save “DeMorganizing” efforts. Selection is through a programmable bit SL1 of the AND/OR logic. The output is active high if SL1 which controls an exclusive-OR gate at the output and active low if SL1 x PALCE16V8 and PALCE16V8Z Families ...

  • Page 6

    ... Feedback is not available on pins 15 and 16 in the combinatorial output mode. 2. This configuration is not available on pins 15 and 16 Registered active high d. Combinatorial I/O active high Note 1 f. Combinatorial output active high Figure 2. Macrocell Configurations PALCE16V8 and PALCE16V8Z Families CLK V CC Note 1 Adjacent I/O pin Note 2 g ...

  • Page 7

    ... PCI AC specifications independent of the design. Zero-Standby Power Mode The PALCE16V8Z features a zero-standby power mode. When none of the inputs switch for an extended period (typically 50 ns), the PALCE16V8Z will go into standby mode, shutting down PALCE16V8 and PALCE16V8Z Families ...

  • Page 8

    ... This saving is illustrated in the I Product-Term Disable On a programmed PALCE16V8Z, any product terms that are not used are disabled. Power is cut off from the product terms so that they do not draw current. As shown in the I graph, product-term disabling results in considerable power savings. This saving is greater at the higher frequencies ...

  • Page 9

    ... LOGIC DIAGRAM CLK SG1 SL1 SG1 SL1 SG1 SL1 SG1 SL1 PALCE16V8 and PALCE16V8Z Families SL0 I SG0 SL0 SL0 I SG1 SL0 SL0 I SG1 SL0 SL0 I SG1 SL0 4 CLK OE 16493E ...

  • Page 10

    ... LOGIC DIAGRAM (CONTINUED GND SG1 SL1 SG1 SL1 SG1 SL1 SG1 SL1 PALCE16V8 and PALCE16V8Z Families CLK SL0 I SG1 SL0 SL0 I SG1 SL0 SL0 I SG1 SL0 SL0 I SG0 SL0 0 11 OE/I 9 16493E-6 (concluded) ...

  • Page 11

    ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

  • Page 12

    CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

  • Page 13

    ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

  • Page 14

    CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

  • Page 15

    ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

  • Page 16

    CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

  • Page 17

    ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C Ambient Temperature with Power Applied . . . . . . . . . . . . . .-55°C ...

  • Page 18

    CAPACITANCE Parameter Symbol Parameter Description C IN Input Capacitance C OUT Output Capacitance Note: 1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified where capacitance may be ...

  • Page 19

    ... Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 4) OUT CC Outputs Open ( mA) OUT V = Max CC and I (or I and I ). OZL IH OZH PALCE16V8Z-12 (Ind Min Max 3. µA V – µA 0.1 OL 2.0 0.9 10 –10 10 –10 –30 –150 MHz MHz 75 Unit µA µ ...

  • Page 20

    ... Test Conditions 2 OUT = 2.0 V Parameter Description 1/( 1/( CNT S CF 1/( and t are defined under best case conditions. Future process improvements PZX PXZ EA ER can be found using the following equation: CF PALCE16V8Z-12 (Ind) Typ Unit 5 ° MHz -12 Min Max Unit 62.5 MHz 77 MHz 100 ...

  • Page 21

    ... Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 4) OUT CC Outputs Open ( mA) OUT V = Max CC and I (or I and I ). OZL IH OZH PALCE16V8Z-15 (Ind Min Max 3. µA V – µA 0.1 OL 2.0 0.9 10 –10 10 –10 –30 –150 MHz MHz 75 Unit µA µ ...

  • Page 22

    ... 1/f (internal feedback) – MAX S 22 Test Conditions 2 5 °C, V OUT = 2 MHz Parameter Description 1/( 1/( CNT S CF 1/( can be found using the following equation: CF PALCE16V8Z-15 (Ind) Typ Unit -15 2 Min Max Unit MHz 58.8 MHz 62.5 MHz ...

  • Page 23

    ... Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 4) OUT CC Outputs Open ( mA) OUT V = Max CC and I (or I and I ). OZL IH OZH PALCE16V8Z-25 (Com’l, Ind Operating Min Max 3. µA V – µA 0.1 OL 2.0 0.9 10 –10 10 –10 –30 –150 MHz MHz 90 Unit ...

  • Page 24

    ... 1/f (internal feedback) – MAX S 24 Test Conditions 2 5 °C, V OUT = 2 MHz Parameter Description 1/( 1/( CNT S CF 1/( can be found using the following equation: CF PALCE16V8Z-25 (Com’l, Ind) Typ Unit -25 2 Min Max Unit 33.3 MHz 50 MHz 50 MHz ...

  • Page 25

    ... Notes 1 Input pulse amplitude 3 Input rise and fall times typical. Input or Feedback Clock V T Registered 16493E-3 Output Input V T Output t WL 16493E-4 d. Input to output disable/enable PXZ V – output disable/enable PALCE16V8 and PALCE16V8Z Families 16493E-5 b. Registered output – 0. 0.5V OL 16493E PZX V ...

  • Page 26

    ... from Don’t Care, Changing, Any Change State Permitted Unknown Does Not Center Apply Line is High- Impedance “Off” State KS000010-PAL Output Test Point Commercial 200 5 pF H-5: 200 PALCE16V8 and PALCE16V8Z Families 16493E-8 R Measured Output Value 2 1.5 V 390 1 – ...

  • Page 27

    ... By utilizing 50% of the device, a midpoint is defined for I estimate the I requirements for a particular design Frequency (MHz) I vs. Frequency CC . From this midpoint, a designer may scale the I CC PALCE16V8 and PALCE16V8Z Families 16V8H-5 16V8H-7 16V8H-10 16V8H-15/25 16V8Z-12/15 16V8Q-10/15/25 16V8Z- 16493E-9 graphs up or down to ...

  • Page 28

    ... Max Operating Temperature Normal Programming Conditions > Programming Programming Pins Only Voltage Detection Typical Input > Provides ESD Protection and Clamping Preload Circuitry Typical Output PALCE16V8 and PALCE16V8Z Families Value Unit 10 Years 20 Years 100 Cycles Positive Programming Overshoot Circuitry Filter Feedback Input 16493E-10 ...

  • Page 29

    ... INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8Z ESD Input Protection Transition and Detection Clamping POWER-UP RESET The PALCE16V8 has been designed with the capability to reset during system power-up. Following power-up, all flip-flops will be reset to LOW. The output state will be HIGH independent of the logic polarity. This feature provides extra flexibility to the designer and is especially valuable in simplifying state machine initialization ...

  • Page 30

    ... Therefore, the measurements can only be used in a similar environment Figure 3. Power-Up Reset Waveform 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air measurement relative to a specific location on the pack- jc PALCE16V8 and PALCE16V8Z Families V CC 16493E-12 Typ PDID PLCC Unit C/W 61 ...

  • Page 31

    ... CONNECTION DIAGRAMS Top View DIP/SOIC CLK GND 10 11 Note: Pin 1 is marked for orientation. PIN DESIGNATIONS CLK = Clock GND = Ground I = Input I/O = Input/Output OE = Output Enable V = Supply Voltage I/O 7 I OE/I 9 16493E-9 PALCE16V8 and PALCE16V8Z Families PLCC 16493E-10 31 ...

  • Page 32

    ... Consult the local Lattice/ /5 Vantis sales office to confirm availability of specific valid combinations and to check on newly released combinations PALCE16V8 and PALCE16V8Z Families PROGRAMMING DESIGNATOR Blank = Initial Algorithm /4 = First Revision /5 = Second Revision (Same Algorithm as /4) OPERATING CONDITIONS ° ...