PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 8

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

most of its internal circuitry. The current will go to almost zero (I
< 15 µA). The outputs will
CC
maintain the states held before the device went into the standby mode. There is no speed
penalty associated with coming out of standby mode.
When any input switches, the internal circuitry is fully enabled, and power consumption returns
to normal. This feature results in considerable power savings for operation at low to medium
frequencies. This saving is illustrated in the I
vs. frequency graph.
CC
Product-Term Disable
On a programmed PALCE16V8Z, any product terms that are not used are disabled. Power is cut
off from the product terms so that they do not draw current. As shown in the I
vs. frequency
CC
graph, product-term disabling results in considerable power savings. This saving is greater at the
higher frequencies.
Further hints on minimizing power consumption can be found in a separate document entitled,
Minimizing Power Consumption with Zero-Power PLDs.
8
PALCE16V8 and PALCE16V8Z Families