PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 28

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

ENDURANCE CHARACTERISTICS
The PALCE16V8 is manufactured using Vantis’ advanced electrically-erasable (EE) CMOS process.
This technology uses an EE cell to replace the fuse link used in bipolar parts. As a result, the
device can be erased and reprogrammed—a feature which allows 100% testing at the factory.
ROBUSTNESS FEATURES
PALCE16V8X-X/5 devices have some unique features that make them extremely robust,
especially when operating in high-speed design environments. Pull-up resistors on inputs and
I/O pins cause unconnected pins to default to a known state. Input clamping circuitry limits
negative overshoot, eliminating the possibility of false clocking caused by subsequent ringing.
A special noise filter makes the programming circuitry completely insensitive to any positive
overshoot that has a pulse width of less than about 100 ns for the /5 versions. Selected /4 devices
are also being retrofitted with these robustness features.
INPUT/OUTPUT EQUIVALENT SCHEMATICS FOR PALCE16V8
28
t
N
DR
Symbol
Min Pattern Data Retention Time
Min Reprogramming Cycles
Protection
Clamping
ESD
and
Parameter
> 50 k
PALCE16V8 and PALCE16V8Z Families
V
C
C
Programming
Pins Only
Provides ESD
Protection and
Clamping
V
CC
Max Storage Temperature
Max Operating Temperature
Normal Programming Conditions
Typical Output
Typical Input
V
CC
Programming
Detection
Test Conditions
Voltage
> 50 k
V
Circuitry
Preload
CC
Overshoot
Positive
Feedback
Filter
Input
Value
Programming
100
10
20
Circuitry
16493E-10
Cycles
Years
Years
Unit