ISL5416KI Intersil, ISL5416KI Datasheet - Page 24

• Manufacturer Part Number: ISL5416KI
• Description: Up/Down Conv Mixer 1.8V 256-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5416KI

• Package: 256BGA
• Operating Supply Voltage: 1.8 V

Serial Data Output
The serial data output control register contains sync position
and polarity (SSYNCA, B, C or D), channel multiplexing, and
scaling controls for the SD1x and SD2x (x = A, B, C or D)
serial outputs (see IWA registers 0*06 - 0*08h).
Serial Data Output Time Slot
Content/Format Registers
These two registers are used to program the content and
format of the serial data output sequence time slots (see
IWA registers 0*07h and 0*08h). There are four data time
slots that make up a serial data output stream. The number
of data bits and data format of each slot is programmable as
well as whether there will be a sync generated with the time
slot (the syncs are only associated with the SD1 serial
outputs). Any of three types of data or zeros can be chosen
for each time slot. Seven bits are used to specify the content
and format of each slot.
Channel Routing Mask
The multiplexing mask bits for each channel (see
Microprocessor Interface Section, IWA register 0*06h bits
19:16 for SD1x or bits 15:12 for SD2x) can be used to enable
that channel’s output to any of the four serial outputs. These
bits control AND gates that mask off the channels, so a zero
disables the channel’s connection to that output.
To configure more than one channel's output onto a serial
data output, the SD1 serial outputs and syncs from each
channel (0,1, 2 and 3) are brought to each of the SD1 serial
output sections and the SD2 serial outputs are brought to
each of the SD2 serial output sections (the syncs are only
associated with the SD1 serial outputs). There, the four
outputs are AND-ed with the multiplexing mask programmed
in the serial data output control registers of channels 0 thru 3
and OR-ed together. By gating off the channels that are not
wanted and delaying the data from each desired channel
appropriately, the channels can be multiplexed into a
common serial output stream. It should be noted that in
order to multiplex multiple channels onto a single serial data
stream the channels to be multiplexed must be synchronous.
Microprocessor Interface
The ISL5416 Microprocessor (µP) interface consists of a 16-
bit bidirectional data bus, P(15:0), three address pins,
ADD(2:0), a write strobe (WR), a read strobe (RD) and a
chip enable (CE). Indirect addressing is used for control and
configuration of the ISL5416.
The processor interface to the ISL5416 is a mixture of direct
and indirect addressing. To minimize the amount of
processor address space and bus routing, there are only
eight 16-bit direct address locations. Two of these are used
to access an internal 32-bit bus. To write data to internal
indirect locations, the data is first written to direct addresses
0 (bits 15:0) and 1 (bits 31:16). The internal address is then
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ISL5416
written to direct address 2. When the address is written, a
synchronization circuit generates an internal write strobe,
synchronized to the clock, to clock the data into the target
register. The synchronization process requires 4 clock
cycles, so data should not be written to direct addresses 0 or
1 for four clock cycles after a write to address 2. To read data
from internal locations, the internal address is first written to
direct address 3. The data can then be read from direct
addresses 0 (15:0) and 1 (31:16). The indirect address
register is shared between direct addresses 2 and 3, with
only writes to address 2 generating write strobes. Because
of this, the address does not have to be re-written to verify a
write unless broadcasting data to more than one channel.
Direct address 2 is used for status when read. The status
bits are defined in Table of Microprocessor Direct
Read/Write Addresses. Direct addresses 4 through 7 are
used for fast read access.
Addresses 4 through 7 (one address per channel) are used
for sequenced read (FIFO-like) addresses. The user can
program the order that the data would be read from the part.
The user can select I, Q, AGC Gain (real time or sampled),
and two types of data from the range control circuit. When a
new output is available, the data type pointer is reset to the
first data type. After each read, the pointer is incremented to
the next data type. To signal a new output on the channel, a
signal can be routed to the CLKO2/INTRPT pin. A channel is
enabled to generate interrupt in address IWA = 0*0Ah, bit 31.
If separate interrupt signals are required for each channel,
the FSYNCX pins can be used.
The indirect address space is divided into top level or global
locations for parameters that are shared between channels
or I/Os, I/O control locations, and channel control
parameters. The global locations are between addresses
0000h and 00FFh. The I/O control locations are between
0100h and 0FFFh. Bits 11, 10, 9, and 8 select I/O busses D,
C, B, and A, respectively. What this means is that by setting
a single address bit of 11:8, the control register is written for
that I/O control section. By setting more than one bit, the
same data is written to the corresponding registers of more
than one I/O control section. Reads must select only one I/O
control section.
Channel control registers are located between addresses
1000h and FFFFh. Bits 15, 14, 13, and 12 select channels 3,
2, 1, and 0, respectively. The user can write to individual
channels or to multiple channels at once by setting the
appropriate channel select bit, 15:12. Read addresses must
specify a single channel.