IDT82P2821BHG IDT, Integrated Device Technology Inc, IDT82P2821BHG Datasheet
IDT82P2821BHG
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82P2821BHG
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Channel High-Density T1/E1/J1 Line Interface Unit IDT82P2821 February 6, 2009 6024 Silver Creek Valley Road, San Jose, California 95138 Telephone: 1-800-345-7015 or 408-284-8200• TWX: 910-338-2070 • FAX: 408-284-2775 © 2009 Integrated Device Technology, Inc. Version 3 Printed in U.S.A. ...
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Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best pos- sible product. IDT does not assume any ...
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TABLE OF CONTENTS ........................................................................................................................................................... 3 LIST OF TABLES .................................................................................................................................................................... 7 LIST OF FIGURES ................................................................................................................................................................... 8 FEATURES ............................................................................................................................................................................. 10 APPLICATIONS...................................................................................................................................................................... 11 DESCRIPTION........................................................................................................................................................................ 11 BLOCK DIAGRAM ................................................................................................................................................................. 12 1 PIN ASSIGNMENT .......................................................................................................................................................... 13 2 PIN DESCRIPTION ......................................................................................................................................................... 18 3 FUNCTIONAL DESCRIPTION ........................................................................................................................................ ...
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IDT82P2821 3.5 DIAGNOSTIC FACILITIES ....................................................................................................................................... 43 3.5.1 Bipolar Violation (BPV) / Code Violation (CV) Detection and BPV Insertion .............................................. 43 3.5.1.1 Bipolar Violation (BPV) / Code Violation (CV) Detection ............................................................. 43 3.5.1.2 Bipolar Violation (BPV) Insertion ................................................................................................. 43 3.5.2 Excessive ...
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IDT82P2821 4.1.4 Per-Channel Software Reset ...................................................................................................................... 70 4.2 MICROPROCESSOR INTERFACE ......................................................................................................................... 70 4.3 POWER UP .............................................................................................................................................................. 71 4.4 HITLESS PROTECTION SWITCHING (HPS) SUMMARY ...................................................................................... 71 5 PROGRAMMING INFORMATION ................................................................................................................................... 74 5.1 REGISTER MAP ...................................................................................................................................................... 74 5.1.1 Global Register ........................................................................................................................................... 74 ...
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IDT82P2821 8.13.4 Parallel Motorola Multiplexed Microprocessor Interface ........................................................................... 142 8.13.4.1 Read Cycle Specification .......................................................................................................... 142 8.13.4.2 Write Cycle Specification .......................................................................................................... 143 8.13.5 Parallel Intel Multiplexed Microprocessor Interface .................................................................................. 144 8.13.5.1 Read Cycle Specification .......................................................................................................... 144 8.13.5.2 Write Cycle Specification .......................................................................................................... ...
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Table-1 Operation Mode Selection ........................................................................................................................................................................... 29 Table-2 Impedance Matching Value in Receive Differential Mode ........................................................................................................................... 30 Table-3 Multiplex Pin Used in Receive System Interface ......................................................................................................................................... 33 Table-4 Multiplex Pin Used in Transmit System Interface ........................................................................................................................................ 35 Table-5 PULS[3:0] Setting in ...
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Figure-1 Functional Block Diagram ............................................................................................................................................................................ 12 Figure-2 640-Pin TEPBGA (Top View) - Outline ........................................................................................................................................................ 13 Figure-3 640-Pin TEPBGA (Top View) - Top Left ...................................................................................................................................................... 14 Figure-4 640-Pin TEPBGA (Top View) - Top Right .................................................................................................................................................... 15 Figure-5 640-Pin TEPBGA (Top View) ...
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IDT82P2821 Figure-49 JTAG Architecture ..................................................................................................................................................................................... 118 Figure-50 JTAG State Diagram ................................................................................................................................................................................. 119 Figure-51 Transmit Clock Timing Diagram ................................................................................................................................................................ 131 Figure-52 Receive Clock Timing Diagram ................................................................................................................................................................. 131 Figure-53 CLKE1 Clock Timing Diagram ................................................................................................................................................................... 132 Figure-54 E1 Jitter Tolerance Performance ............................................................................................................................................................... 134 ...
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FEATURES Integrates 21+1 channels T1/E1/J1 short haul line interface units for 100 Ω T1, 120 Ω E1, 110 Ω J1 twisted pair cable and 75 Ω E1 coaxial cable applications Per-channel configurable Line Interface options • Supports various line interface ...
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IDT82P2821 APPLICATIONS SDH/SONET multiplexers Central office or PBX (Private Branch Exchange) Digital access cross connects Remote wireless modules Microwave transmission systems DESCRIPTION The IDT82P2821 is a 21+1 channels high-density T1/E1/J1 short haul Line Interface Unit. Each channel of the IDT82P2821 ...
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IDT82P2821 BLOCK DIAGRAM Block Diagram 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Figure-1 Functional Block Diagram 12 TDO TDI TCK TMS TRST CLKB CLKA REFB REFA CLKE1 CLKT1 MCKSEL[3:0] MCLK A[10:0] D[7:0] SDO/ACK /READY SDI/ SCLK/ DS/RD ALE/AS ...
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IDT82P2821 1 PIN ASSIGNMENT Figure-2 shows the outline of the pin assignment. For a clearer description, four segments are divided in this figure and the details of each are shown from Figure-3 to Figure- ...
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IDT82P2821 GNDA VDDA TTIP18 TTIP17 TRING TRING B GNDA VDDA 18 17 VDDT VDDT VDDT C TTIP19 TRING D GNDT RTIP18 RTIP17 19 TRING RRING VDDR E GNDT VDDT ...
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IDT82P2821 TDN16/ RCLK16/ RD15/ TDN14/ A TMF16 RMF16 RDP15 TMF14 TD16/ RDN16/ TCLK15/ TD14/ B TDP16 RMF16 TDN15 TDP14 RCLK17/ RD16/ TDN15/ RCLK15/ C RMF17 RDP16 TMF15 RMF15 TCLK16/ TD15/ RDN15 TDN16 TDP15 RMF15 ...
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IDT82P2821 TRING3 GNDT NC VDDA U TTIP3 GNDT NC RRING2 VDDR3 RTIP2 W TRING4 VDDT4 NC VDDA Y TTIP4 VDDT5 NC RRING4 AA TTIP5 TRING5 GNDT RTIP4 AB GNDA GNDT NC ...
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IDT82P2821 GNDD GNDD GNDD GNDD U GNDD GNDD GNDD GNDD V GNDD GNDD GNDD GNDD W GNDD GNDD GNDD GNDD VDDIO VDDIO VDDIO VDDD MCKSEL AF NC LLOS LLOS0 ...
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IDT82P2821 2 PIN DESCRIPTION Name RTIPn Input P3, R5, V4, W5, AA4, AB5, AE28, AE26, AA26, W28, T28, R26, L28, RRINGn L26, G26, F28, D6, D4, D3, G4, H5, (n=0~21) N3, P5, U4, V5, Y4, AA5, AD28, ...
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IDT82P2821 Name RDn / RDPn Output AH9, AC4, AG1, AH3, AH6, AK8, AK20, AH21, AH24, AK26, AH29, (n=0~21) A27, A24, C23, C20, A18, C17, B15, D14, B12, D11, D8 RDNn / RMFn Output AG9, AD1, AH1, AG3, ...
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IDT82P2821 Name RCLKn / RMFn Output AK10, AD2, AH2, AK4, AK7, AH8, AH20, AK22, AK25, AH26, AG29, (n=0~21) A28, C25, A23, A20, C19, A17, C16, B14, D13, B11, B8 LLOS Output LLOS0 Output Pin Description 21(+1) CHANNEL ...
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IDT82P2821 Name TDn / TDPn Input AG8, AC1, AF1, AG2, AG5, AJ7, AJ19, AG20, AG23, AJ25, AJ28, (n=0~21) D27, D24, B22, B19, D18, B16, A14, C13, A11, C10, C7 TDNn / TMFn Input / Output AK9, AC2, ...
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IDT82P2821 Name MCLK Input MCKSEL[0] Input MCKSEL[1] MCKSEL[2] MCKSEL[3] CLKT1 Output CLKE1 Output Pin Description 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Pin No. Clock AK19 MCLK: Master Clock Input MCLK provides a stable reference timing for ...
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IDT82P2821 Name REFA Output REFB Output CLKA Input CLKB Input VCOM[0] Output VCOM[1] VCOMEN Input (Pull-Down) REF - RIM Input (Pull-Down) Pin Description 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Pin No. AK18 REFA: Reference Clock Output ...
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IDT82P2821 Name Input TEHWE Input (Pull-Up) TEHW Input (Pull-Up) GPIO[0] Output / Input GPIO[1] Input RST INT Output Input CS P/S Input INT/MOT Input (Pull-Up) Pin Description 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Pin No. ...
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IDT82P2821 Name Input (Pull-Up) ALE / AS Input SCLK / Input SDI / R Input Pin Description 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Pin No. AF15 IM: Interface Mode Selection ...
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IDT82P2821 Name SDO / ACK / RDY Output D[0] Output / Input D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] Input A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] Input TRST Pull-Down TMS Input Pull-up ...
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IDT82P2821 Name TDI Input Pull-up TDO Output VDDIO E7, E8, E10, E11, E12, E21, E22, E23, E24, E25, AE9, AE10, AE15, AE16, AE17, AE18, AE22, AE23, VDDA A2, B2, J26, K27, L4, L27, M4, M26, T4, W4, ...
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IDT82P2821 Name GNDT B5, B6, C5, D2, D28, E2, H28, H29, J3, J5, J28, K3, K5, L3, M3, M28, N28, N29, T2, U2, U28, V28, V29, W29, AA3, AB2, AB28, AD29, AE29 A8, ...
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IDT82P2821 3 FUNCTIONAL DESCRIPTION 3 MODE SELECTION The IDT82P2821 can be configured to T1/J1 mode or E1 mode globally per-channel basis. The configuration is determined by the TEHWE pin, the TEHW pin ...
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IDT82P2821 When RIM is low, only External Impedance Matching is supported for all 22 receivers and the per-channel impedance matching configuration bits - the R_TERM[2:0] bits (b2~0, RCF0,...) and the R120IN bit (b4, RCF0,...) - are ignored. When RIM is ...
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IDT82P2821 RTIPn Rr/2 6.0Vpp Rr/2 RRINGn VCOM1 10 µF 1. Two Rr/2 resistors should be connected to VCOM[1:0] that are Note: coupled to ground via a 10 µF capacitor, which provide 60 Ω common mode input resistance this ...
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IDT82P2821 3.2.2 EQUALIZER The equalizer compensates high frequency attenuation to enhance receive sensitivity. 3.2.2.1 Line Monitor In both T1/J1 and E1 short haul applications, the Protected Non- Intrusive Monitoring per T1.102 can be performed between two devices. The monitored channel ...
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IDT82P2821 3.2.3 SLICER The Slicer is used to generate a standard amplitude mark or a space according to the amplitude of the input signals. The input signal is sliced at 50% of the peak value. 3.2.4 R CLOCK & DATA ...
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IDT82P2821 3.2.7 RECEIVER POWER DOWN Set the R_OFF bit (b5, RCF0,...) to ‘1’ will power down the corre- sponding receiver. In this way, the corresponding receive circuit is turned off and the RTIPn/RRINGn pins are forced to High-Z state. The ...
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IDT82P2821 Table-4 Multiplex Pin Used in Transmit System Interface Multiplex Pin Used On Transmit System Transmit System Interface TDn / TDPn 1 Single Rail NRZ Format TDn 1 Dual Rail NRZ Format TDPn 1 Dual Rail RZ Format TDPn Note: ...
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IDT82P2821 Table-5 PULS[3:0] Setting in T1/J1 Mode Cable Conditions DSX1 - 0 ~ 133 ft DSX1 - 133 ~ 266 ft DSX1 - 266 ~ 399 ft DSX1 - 399 ~ 533 ft DSX1 - 533 ~ 655 ft J1 ...
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IDT82P2821 3.3.4.2 User-Programmable Arbitrary Waveform When the PULS[3:0] bits (b3~0, PULS,...) are set to ‘1XXX’, user- programmable arbitrary waveform will be used in the corresponding channel. Each waveform shape can extend up to divided into 20 sub-phases that are addressed ...
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IDT82P2821 Table-7 Transmit Waveform Value for 133 SAMP[4:0] WDAT[6:0] 17H 27H 27H 26H Table-8 Transmit Waveform Value for T1 133 ~ 266 ft SAMP[4: WDAT[6:0] 1BH 2EH 2CH ...
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IDT82P2821 3.3.5 LINE DRIVER The Line Driver can be set to High-Z for protection or in redundant applications. The following two ways will set the Line Driver to High-Z: • Setting the OE pin to low will globally set all ...
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IDT82P2821 TTIPn TRINGn Figure-19 Transmit Differential Line Interface with Twisted Pair Cable (with Transformer) TTIPn TRINGn Figure-20 Transmit Differential Line Interface with Co- axial Cable (with transformer) TTIPn IM TRINGn Note: In this mode, ...
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IDT82P2821 3.3.7 TRANSMITTER POWER DOWN Set the T_OFF bit (b5, TCF0,...) to ‘1’ will power down the corre- sponding transmitter. In this way, the corresponding transmit circuit is turned off. The pins on the transmit line interface (including TTIPn and ...
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IDT82P2821 3.4 JITTER ATTENUATOR (RJA & TJA) Two Jitter Attenuators are provided for each channel of receiver and transmitter. Each Jitter Attenuator can be enabled or disabled, as deter- mined by the RJA_EN/TJA_EN bit (b3, RJA/TJA,...) respectively. Each Jitter Attenuator ...
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IDT82P2821 3.5 DIAGNOSTIC FACILITIES The diagnostic facilities include: • BPV (Bipolar Violation (Code Violation) detection and BPV insertion; • EXZ (Excessive Zero) detection; • LOS (Loss Of Signal) detection; • AIS (Alarm Indication Signal) detection and generation; • ...
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IDT82P2821 3.5.3 LOSS OF SIGNAL (LOS) DETECTION The IDT82P2821 detects three kinds of LOS: • LLOS: Line LOS, detected in the receive path; • SLOS: System LOS, detected in the transmit system side; • TLOS: Transmit LOS, detected in the ...
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IDT82P2821 3.5.3.2 System LOS (SLOS) SLOS can only be detected when the transmit system interface is in Dual Rail NRZ Format mode or in Dual Rail RZ Format mode. The amplitude and density of the data input from the transmit ...
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IDT82P2821 3.5.3.3 Transmit LOS (TLOS) The amplitude and density of the data output on the transmit line side are monitored. When the amplitude of the data is less than a certain voltage for a certain period, TLOS is declared. The ...
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IDT82P2821 3.5.4 ALARM INDICATION SIGNAL (AIS) DETECTION AND GEN- ERATION 3.5.4.1 Alarm Indication Signal (AIS) Detection AIS is monitored in both the receive path and the transmit path. When the mark density in the received data or in the data ...
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IDT82P2821 3.5.5 PRBS, QRSS, ARB AND IB PATTERN GENERATION AND DETECTION The pattern includes: Pseudo Random Bit Sequence (PRBS), Quasi- Random Signal Source (QRSS), Arbitrary Pattern (ARB) and Inband Loopback (IB). 3.5.5.1 Pattern Generation The pattern can be generated in ...
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IDT82P2821 3.5.5.2 Pattern Detection Data received from the line side or data input from the transmit system side may be extracted for pattern detection. The direction of data extraction is determined by the PD_POS bit (b3, PD,...). One of PRBS ...
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IDT82P2821 Inband Loopback (IB) Detection The IB detection is in compliance with ANSI T1.403. The extracted data is used to compare with the target IB code. The length of the target activate/deactivate IB code can bits, ...
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IDT82P2821 Automatic Error Counter Updating (CNT_MD = 1) Counting No One second expired? (TMOV_IS = 1 ?) Yes Data in the Error Counter transfers to the ERRCH & ERRCL registers The Error Counter is cleared TMOV_IS is cleared after a ...
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IDT82P2821 3.5.7 RECEIVE /TRANSMIT MULTIPLEX FUNCTION (RMF / TMF) INDICATION 3.5.7.1 RMFn Indication In Receive Single Rail NRZ Format mode, the RDNn/RMFn pin is used as RMFn. In Receive Dual Rail Sliced mode, the RCLKn/RMFn pin is used as RMFn. ...
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IDT82P2821 3.5.7.2 TMFn Indication In Transmit Single Rail NRZ Format mode and Transmit Dual Rail RZ Format mode, the TDNn/TMFn pin is used as TMFn. Refer to Table-4 Multiplex Pin Used in Transmit System Interface for details. Table-22 TMFn Indication ...
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IDT82P2821 3.5.8 LOOPBACK There are four kinds of loopback: • Analog Loopback • Remote Loopback • Digital Loopback • Dual Loopback Refer to Figure-1 for loopback location. 3.5.8.1 Analog Loopback Analog Loopback is enabled by the ALP bit (b0, LOOP,...). ...
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IDT82P2821 3.5.8.2 Remote Loopback Remote Loopback can be configured manually or automatically. Either manual Remote Loopback configuration or automatic Remote Loopback configuration will enable Remote Loopback. Manual Remote Loopback is enabled by the RLP bit (b1, LOOP,...). Automatic Remote Loopback ...
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IDT82P2821 3.5.8.3 Digital Loopback The Digital Loopback can be configured manually or automatically. Either manual Digital Loopback configuration or automatic Digital Loop- back configuration will enable Digital Loopback. Manual Digital Loopback is enabled by the DLP bit (b2, LOOP,...). Automatic ...
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IDT82P2821 3.5.8.4 Dual Loopback Dual Loopback refers to the simultaneous implementation of Remote Loopback and Digital Loopback. Two kinds of combinations are supported: • Manual Remote Loopback + Manual Digital Loopback; • Manual Remote Loopback + Automatic Digital Loopback. Note ...
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IDT82P2821 LLOS, AIS detection Remote Loopback X AIS generation Figure-35 Priority Of Diagnostic Facilities During Manual Remote Loopback + Manual Digital Loopback LLOS, AIS detection Remote Loopback X AIS generation Figure-36 Priority Of Diagnostic Facilities During Manual Remote Loopback + ...
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IDT82P2821 3.5.9 CHANNEL 0 MONITORING Channel special channel. It can be used in normal operation as the other 21 channels can be used as a monitoring channel. Channel 0 supports G.772 Monitoring and Jitter Measurement. ...
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IDT82P2821 3.5.9.2 Jitter Measurement (JM) The RJA of channel 0 consists of a Jitter Measurement (JM) module. When the RJA is enabled in channel 0, the JM is used to measure the positive and negative peak value of the demodulated ...
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IDT82P2821 3.6 CLOCK INPUTS AND OUTPUTS The IDT82P2821 provides two kinds of clock outputs: • Free running clock outputs on CLKT1 and CLKE1 • Receiver clock outputs on REFA and REFB - selected from any of the 22 recovered line ...
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IDT82P2821 3.6.2 CLOCK OUTPUTS ON REFA/REFB The outputs on REFA and REFB can be enabled or disabled, as determined by the REFA_EN bit (b6, REFA) and the REFB_EN bit (b6, REFB) respectively. When the output is disabled, REFA/REFB is in ...
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IDT82P2821 Recovered clock of one of the 22 channels JA_BYPAS = Clock is derived from the output of RJA Output the selected clock on REFA Note *: '000' and '011' are reserved for FREQ[2:0] when REFA is ...
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IDT82P2821 Recovered clock of one of the 22 channels JA_BYPAS = Clock is derived from the output of RJA Figure-41 REFB Output Options in Normal Operation Output on REFA is free running (locked to MCLK). The frequency ...
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IDT82P2821 Output on REFA is free running (locked to MCLK). The frequency is programmed in FREQ[2:0] *. Note *: '000' and '011' are reserved for FREQ[2:0] when REFA is free running. Figure-43 REFA Output in No CLKA Condition (When CLKA ...
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IDT82P2821 3.6.3 MCLK, MASTER CLOCK INPUT MCLK provides a stable reference timing for the IDT82P2821. MCLK should be a clock with +/-32 ppm (in T1/J1 mode) or +/-50 ppm (in E1 mode) accuracy. The clock frequency of MCLK is set ...
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IDT82P2821 3.7 INTERRUPT SUMMARY There are altogether 20 kinds of interrupt sources as listed in Table- 25. Among them, No.1 to No.19 are per-channel interrupt sources, while No global interrupt source. For interrupt sources from No.1 to ...
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IDT82P2821 No Functional Description 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT INT active Read TMOV_IS TMOV_IS = 1 ? Yes Serve the interrupt. Read the interrupt status bits Write '1' to clear TMOV_IS. in the corresponding channel. Find the interrupt ...
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IDT82P2821 4 MISCELLANEOUS 4.1 RESET The reset operation resets all registers, state machines as well as I/O pins to their default value or status. The IDT82P2821 provides 4 kinds of reset: • Power-on reset; • Hardware reset; • Global software ...
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IDT82P2821 4.1.1 POWER-ON RESET Power-on reset is initiated during power-up. When all VDD inputs (1.8V and 3.3V) reach approximately 60% of the standard value of VDD, power-on reset begins. If MCLK is applied, power-on reset will complete within 1 ms ...
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IDT82P2821 4.3 POWER UP No power up sequencing for the VDD inputs (1.8 V and 3.3 V) has to be provided for the IDT82P2821. A Power-on reset will be initiated during power up. Refer to Section 4.1 Reset. 4.4 HITLESS ...
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IDT82P2821 Hot switch control Rx: Fully Internal Impedance Matching mode. In this mode, there is no external resistor required. The R_TERM[2:0] bits (b2~0, RCF0,...) setting is as follows: ‘000’ for T1 100 Ω twisted pair cable, ‘001’ for J1 110 ...
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IDT82P2821 Hot switch control Rx: 75 Ω External Impedance Matching mode. In this mode, there is no external resistor required. The RIM pin should be left open and the configuration of the R_TERM[2:0] bits (b2~0, RCF0,...) is ignored. Tx: 75 ...
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IDT82P2821 5 PROGRAMMING INFORMATION 5.1 REGISTER MAP 5.1.1 GLOBAL REGISTER Address Register Name (Hex) Common Control 000 ID - Device ID Register 040 RST - Global Reset Register 080 GCF - Global Configuration Register 0C0 MON - G.772 Monitor Configura- ...
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IDT82P2821 5.1.2 PER-CHANNEL REGISTER Except for registers 7E5~7E9, which are channel 0 related registers, only the address of channel 1 is listed in the ‘Address (Hex)’ column of the following table. For the addresses of the other channels, refer to ...
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IDT82P2821 Address Register Name (Hex) 011 PD - Pattern Detection Control Register 012 ARBL - Arbitrary Pattern Gener- ation / Detection Low-Byte Reg- ister 013 ARBM - Arbitrary Pattern Gen- eration / Detection Middle-Byte Register 014 ARBH - Arbitrary Pattern ...
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IDT82P2821 Address Register Name (Hex) Counter 023 ERRCL - Error Counter Low- Byte Register 024 ERRCH - Error Counter High- Byte Register Jitter Measurement (channel 0 Only) 7E5 JM - Jitter Measurement Config- uration For Channel 0 Register 7E6 JIT_PL ...
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IDT82P2821 5.2 REGISTER DESCRIPTION 5.2.1 GLOBAL REGISTER ID - Device ID Register Address: 000H Type: Read Default Value: 20H 7 6 ID7 ID6 Bit Name ID[7:0] The ID[7:0] bits are pre-set. The ID[7:4] bits represent the device ...
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IDT82P2821 GCF - Global Configuration Register Address: 080H Type: Read / Write Default Value: 03H Bit Name Reserved. 4 COPY When the per-channel register of one channel is written, this bit determines ...
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IDT82P2821 MON - G.772 Monitor Configuration Register Address: 0C0H Type: Read / Write Default Value: 00H Bit Name Reserved MON[5:0] These bits determine whether the G.772 Monitor is implemented. ...
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IDT82P2821 GPIO - General Purpose I/O Pin Definition Register Address: 100H Type: Read / Write Default Value: 0FH Bit Name Reserved. 3 LEVEL1 When the GPIO1 pin is defined as output, this ...
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IDT82P2821 CLKG - CLKT1 & CLKE1 Generation Control Register Address: 1C0H Type: Read / Write Default Value: 0FH Bit Name Reserved. 3 CLKE1_EN This bit controls whether the output on the CLKE1 ...
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IDT82P2821 3 FREE This bit is valid only when the selected clock source for REFA passes the internal Frequency Synthesizer In normal operation: 0: Output the clock which is locked to the selected clock source and the frequency is programmed ...
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IDT82P2821 REFA - REFA Clock Sources Configuration Register Address: 240H Type: Read / Write Default Value: 41H REFA_EN Bit Name 7 - Reserved. 6 REFA_EN This bit controls whether the output on the REFA pin is enabled. ...
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IDT82P2821 INTCH1 - Interrupt Requisition Source Register 1 Address: 2C0H Type: Read / Write Default Value: 00H 7 6 INT_CH8 INT_CH7 Bit Name INT_CH[8:1] These bits indicate whether there is an interrupt generated in the corresponding channel. ...
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IDT82P2821 INTCH4 - Interrupt Requisition Source Register 4 Address: 380H Type: Read / Write Default Value: 00H 7 6 INT_CH0 - Bit Name 7 INT_CH0 This bit indicates whether there is an interrupt generated in channel interrupt ...
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IDT82P2821 5.2.2 PER-CHANNEL REGISTER CHCF - Channel Configuration Register Address: 001H, 041H, 081H, 0C1H, 101H, 141H, 181H, 1C1H, (CH1~CH8) 201H, 241H, 281H, 2C1H, 301H, 341H, 381H, 3C1H, (CH9~CH16) 401H, 441H, 481H, 4C1H, 501H, (CH17~CH21) 7C1H (CH0) Type: Read / Write ...
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IDT82P2821 RJA - Receive Jitter Attenuation Configuration Register Address: 003H, 043H, 083H, 0C3H, 103H, 143H, 183H, 1C3H, (CH1~CH8) 203H, 243H, 283H, 2C3H, 303H, 343H, 383H, 3C3H, (CH9~CH16) 403H, 443H, 483H, 4C3H, 503H, (CH17~CH21) 7C3H (CH0) Type: Read / Write Default ...
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IDT82P2821 TCF0 - Transmit Configuration Register 0 Address: 004H, 044H, 084H, 0C4H, 104H, 144H, 184H, 1C4H, (CH1~CH8) 204H, 244H, 284H, 2C4H, 304H, 344H, 384H, 3C4H, (CH9~CH16) 404H, 444H, 484H, 4C4H, 504H, (CH17~CH21) 7C4H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 TCF1 - Transmit Configuration Register 1 Address: 005H, 045H, 085H, 0C5H, 105H, 145H, 185H, 1C5H, (CH1~CH8) 205H, 245H, 285H, 2C5H, 305H, 345H, 385H, 3C5H, (CH9~CH16) 405H, 445H, 485H, 4C5H, 505H, (CH17~CH21) 7C5H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 PULS - Transmit Pulse Configuration Register Address: 006H, 046H, 086H, 0C6H, 106H, 146H, 186H, 1C6H, (CH1~CH8) 206H, 246H, 286H, 2C6H, 306H, 346H, 386H, 3C6H, (CH9~CH16) 406H, 446H, 486H, 4C6H, 506H, (CH17~CH21) 7C6H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 SCAL - Amplitude Scaling Control Register Address: 007H, 047H, 087H, 0C7H, 107H, 147H, 187H, 1C7H, (CH1~CH8) 207H, 247H, 287H, 2C7H, 307H, 347H, 387H, 3C7H, (CH9~CH16) 407H, 447H, 487H, 4C7H, 507H, (CH17~CH21) 7C7H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 AWG1 - Arbitrary Waveform Generation Control Register 1 Address: 009H, 049H, 089H, 0C9H, 109H, 149H, 189H, 1C9H, (CH1~CH8) 209H, 249H, 289H, 2C9H, 309H, 349H, 389H, 3C9H, (CH9~CH16) 409H, 449H, 489H, 4C9H, 509H, (CH17~CH21) 7C9H (CH0) Type: Read / Write ...
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IDT82P2821 RCF0 - Receive Configuration Register 0 Address: 00AH, 04AH, 08AH, 0CAH, 10AH, 14AH, 18AH, 1CAH, (CH1~CH8) 20AH, 24AH, 28AH, 2CAH, 30AH, 34AH, 38AH, 3CAH, (CH9~CH16) 40AH, 44AH, 48AH, 4CAH, 50AH, (CH17~CH21) 7CAH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 RCF1 - Receive Configuration Register 1 Address: 00BH, 04BH, 08BH, 0CBH, 10BH, 14BH, 18BH, 1CBH, (CH1~CH8) 20BH, 24BH, 28BH, 2CBH, 30BH, 34BH, 38BH, 3CBH, (CH9~CH16) 40BH, 44BH, 48BH, 4CBH, 50BH, (CH17~CH21) 7CBH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 RCF2 - Receive Configuration Register 2 Address: 00CH, 04CH, 08CH, 0CCH, 10CH, 14CH, 18CH, 1CCH, (CH1~CH8) 20CH, 24CH, 28CH, 2CCH, 30CH, 34CH, 38CH, 3CCH, (CH9~CH16) 40CH, 44CH, 48CH, 4CCH, 50CH, (CH17~CH21) 7CCH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 LOS - LOS Configuration Register Address: 00DH, 04DH, 08DH, 0CDH, 10DH, 14DH, 18DH, 1CDH, (CH1~CH8) 20DH, 24DH, 28DH, 2CDH, 30DH, 34DH, 38DH, 3CDH, (CH9~CH16) 40DH, 44DH, 48DH, 4CDH, 50DH, (CH17~CH21) 7CDH (CH0) Type: Read / Write Default Value: 15H ...
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IDT82P2821 TDLOS[1:0] These bits select the period. When the amplitude of the data is less than a certain voltage for the period, TLOS is declared. The voltage is determined by the TALOS bits (b3~2, LOS,...). 00: 16-pulse. ...
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IDT82P2821 AISG - AIS Generation Control Register Address: 00FH, 04FH, 08FH, 0CFH, 10FH, 14FH, 18FH, 1CFH, (CH1~CH8) 20FH, 24FH, 28FH, 2CFH, 30FH, 34FH, 38FH, 3CFH, (CH9~CH16) 40FH, 44FH, 48FH, 4CFH, 50FH, (CH17~CH21) 7CFH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 PG - Pattern Generation Control Register Address: 010H, 050H, 090H, 0D0H, 110H, 150H, 190H, 1D0H, (CH1~CH8) 210H, 250H, 290H, 2D0H, 310H, 350H, 390H, 3D0H, (CH9~CH16) 410H, 450H, 490H, 4D0H, 510H, (CH17~CH21) 7D0H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 PD - Pattern Detection Control Register Address: 011H, 051H, 091H, 0D1H, 111H, 151H, 191H, 1D1H, (CH1~CH8) 211H, 251H, 291H, 2D1H, 311H, 351H, 391H, 3D1H, (CH9~CH16) 411H, 451H, 491H, 4D11H, 511H, (CH17~CH21) 7D1H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 ARBL - Arbitrary Pattern Generation / Detection Low-Byte Register Address: 012H, 052H, 092H, 0D2H, 112H, 152H, 192H, 1D2H, (CH1~CH8) 212H, 252H, 292H, 2D2H, 312H, 352H, 392H, 3D2H, (CH9~CH16) 412H, 452H, 492H, 4D2H, 512H, (CH17~CH21) 7D2H (CH0) Type: Read / ...
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IDT82P2821 IBL - Inband Loopback Control Register Address: 015H, 055H, 095H, 0D5H, 115H, 155H, 195H, 1D5H, (CH1~CH8) 215H, 255H, 295H, 2D5H, 315H, 355H, 395H, 3D5H, (CH9~CH16) 415H, 455H, 495H, 4D5H, 515H, (CH17~CH21) 7D5H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 IBDA - Inband Loopback Detection Target Activate Code Definition Register Address: 017H, 057H, 097H, 0D7H, 117H, 157H, 197H, 1D7H, (CH1~CH8) 217H, 257H, 297H, 2D7H, 317H, 357H, 397H, 3D7H, (CH9~CH16) 417H, 457H, 497H, 4D7H, 517H, (CH17~CH21) 7D7H (CH0) Type: Read ...
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IDT82P2821 LOOP - Loopback Control Register Address: 019H, 059H, 099H, 0D9H, 119H, 159H, 199H, 1D9H, (CH1~CH8) 219H, 259H, 299H, 2D9H, 319H, 359H, 399H, 3D9H, (CH9~CH16) 419H, 459H, 499H, 4D9H, 519H, (CH17~CH21) 7D9H (CH0) Type: Read / Write Default Value: 00H ...
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IDT82P2821 INTES - Interrupt Trigger Edges Select Register Address: 01AH, 05AH, 09AH, 0DAH, 11AH, 15AH, 19AH, 1DAH, (CH1~CH8) 21AH, 25AH, 29AH, 2DAH, 31AH, 35AH, 39AH, 3DAH, (CH9~CH16) 41AH, 45AH, 49AH, 4DAH, 51AH, (CH17~CH21) 7DAH (CH0) Type: Read / Write Default ...
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IDT82P2821 INTM0 - Interrupt Mask Register 0 Address: 01BH, 05BH, 09BH, 0DBH, 11BH, 15BH, 19BH, 1DBH, (CH1~CH8) 21BH, 25BH, 29BH, 2DBH, 31BH, 35BH, 39BH, 3DBH, (CH9~CH16) 41BH, 45BH, 49BH, 4DBH, 51BH, (CH17~CH21) 7DBH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 INTM1 - Interrupt Mask Register 1 Address: 01CH, 05CH, 09CH, 0DCH, 11CH, 15CH, 19CH, 1DCH, (CH1~CH8) 21CH, 25CH, 29CH, 2DCH, 31CH, 35CH, 39CH, 3DCH, (CH9~CH16) 41CH, 45CH, 49CH, 4DCH, 51CH, (CH17~CH21) 7DCH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 INTM2 - Interrupt Mask Register 2 Address: 01DH, 05DH, 09DH, 0DDH, 11DH, 15DH, 19DH, 1DDH, (CH1~CH8) 21DH, 25DH, 29DH, 2DDH, 31DH, 35DH, 39DH, 3DDH, (CH9~CH16) 41DH, 45DH, 49DH, 4DDH, 51DH, (CH17~CH21) 7DDH (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 STAT0 - Status Register 0 Address: 01EH, 05EH, 09EH, 0DEH, 11EH, 15EH, 19EH, 1DEH, (CH1~CH8) 21EH, 25EH, 29EH, 2DEH, 31EH, 35EH, 39EH, 3DEH, (CH9~CH16) 41EH, 45EH, 49EH, 4DEH, 51EH, (CH17~CH21) 7DEH (CH0) Type: Read Default Value: 00H 7 6 ...
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IDT82P2821 STAT1 - Status Register 1 Address: 01FH, 05FH, 09FH, 0DFH, 11FH, 15FH, 19FH, 1DFH, (CH1~CH8) 21FH, 25FH, 29FH, 2DFH, 31FH, 35FH, 39FH, 3DFH, (CH9~CH16) 41FH, 45FH, 49FH, 4DFH, 51FH, (CH17~CH21) 7DFH (CH0) Type: Read Default Value: 00H 7 6 ...
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IDT82P2821 INTS0 - Interrupt Status Register 0 Address: 020H, 060H, 0A0H, 0E0H, 120H, 160H, 1A0H, 1E0H, (CH1~CH8) 220H, 260H, 2A0H, 2E0H, 320H, 360H, 3A0H, 3E0H, (CH9~CH16) 420H, 460H, 4A0H, 4E0H, 520H, (CH17~CH21) 7E0H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 INTS1 - Interrupt Status Register 1 Address: 021H, 061H, 0A1H, 0E1H, 121H, 161H, 1A1H, 1E1H, (CH1~CH8) 221H, 261H, 2A1H, 2E1H, 321H, 361H, 3A1H, 3E1H, (CH9~CH16) 421H, 461H, 4A1H, 4E1H, 521H, (CH17~CH21) 7E1H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 INTS2 - Interrupt Status Register 2 Address: 022H, 062H, 0A2H, 0E2H, 122H, 162H, 1A2H, 1E2H, (CH1~CH8) 222H, 262H, 2A2H, 2E2H, 322H, 362H, 3A2H, 3E2H, (CH9~CH16) 422H, 462H, 4A2H, 4E2H, 522H, (CH17~CH21) 7E2H (CH0) Type: Read / Write Default Value: ...
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IDT82P2821 ERRCL - Error Counter Low-Byte Register Address: 023H, 063H, 0A3H, 0E3H, 123H, 163H, 1A3H, 1E3H, (CH1~CH8) 223H, 263H, 2A3H, 2E3H, 323H, 363H, 3A3H, 3E3H, (CH9~CH16) 423H, 463H, 4A3H, 4E3H, 523H, (CH17~CH21) 7E3H (CH0) Type: Read Default Value: 00H 7 ...
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IDT82P2821 JM - Jitter Measurement Configuration For Channel 0 Register Address: 7E5H Type: Read / Write Default Value: 00H Bit Name Reserved. 2 JM_STOP This bit is valid only when the JM_MD ...
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IDT82P2821 JIT_NL - Negative Peak Jitter Measurement Low-Byte Register Address: 7E8H Type: Read Default Value: 00H 7 6 JIT_N7 JIT_N6 Bit Name JIT_N[7:0] These bits, together with the JIT_N[11:8] bits, reflect the greatest negative peak value of ...
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IDT82P2821 6 JTAG The IDT82P2821 supports the digital Boundary Scan Specification as described in the IEEE 1149.1 standards. The boundary scan architecture consists of data and instruction registers plus a Test Access Port (TAP) controller. The control of the TAP ...
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IDT82P2821 1 Test-logic Reset 0 0 Run Test/Idle JTAG 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT 1 1 Select- Capture- Shift- Exit1- Pause- Exit2-DR 1 Update- Figure-50 JTAG ...
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IDT82P2821 7 THERMAL MANAGEMENT The device is designed to operate over the industry temperature range -40°C ~ +85°C. To ensure the functionality and reliability of the device, the maximum junction temperature, T 125°C. In some applications, the device will consume ...
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IDT82P2821 8 PHYSICAL AND ELECTRICAL SPECIFICATIONS 8.1 ABSOLUTE MAXIMUM RATINGS Symbol VDDD Digital Core Power Supply VDDA Analog Core Power Supply VDDIO I/O Power Supply VDDT0~21 Power Supply for Transmitter Driver VDDR0~21 Power Supply for Receiver Input Voltage, Any Digital ...
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IDT82P2821 8.2 RECOMMENDED OPERATING CONDITIONS Symbol T Operating Temperature Range op VDDIO Digital I/O Power Supply VDDA Analog Core Power Supply VDDD Digital Core Power Supply VDDT Power Supply for Transmitter Driver VDDR Power Supply for Receiver V Input Low ...
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IDT82P2821 8.3 DEVICE POWER CONSUMPTION AND DISSIPATION (TYPICAL) Total Consumption (W) Mode Parameter 1.8 V E1/120 Ω PRBS 0.23 100% ones 0.23 E1/75 Ω PRBS 0.23 100% ones 0.23 T1/100 Ω QRSS 0.18 100% ones 0.18 J1/110 Ω QRSS 0.18 ...
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IDT82P2821 8.4 DEVICE POWER CONSUMPTION AND DISSIPATION (MAXIMUM) Mode Parameter E1/120 Ω PRBS 100% ones E1/75 Ω PRBS 100% ones T1/100 Ω QRSS 100% ones J1/110 Ω QRSS 100% ones Note: 1. Test conditions: VDDx (maximum °C operating ...
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IDT82P2821 8.5 D.C. CHARACTERISTICS @ TA = -40 to +85 °C, VDDIO = 3.3 V ± 5%, VDDD = 1.8 V ± 5% Symbol Parameter V Output Low Voltage OL V Output High Voltage OH V Schmitt Trigger Input Low ...
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IDT82P2821 8.6 E1 RECEIVER ELECTRICAL CHARACTERISTICS Parameter Receiver Sensitivity of Receive Differen- tial mode with Cable Loss @ 1024 KHz Receiver Sensitivity of Receive Single Ended mode with Cable Loss @ 1024 kHz Signal to Noise Interference Margin Analog LOS ...
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IDT82P2821 8.7 T1/J1 RECEIVER ELECTRICAL CHARACTERISTICS Parameter Receiver Sensitivity of Receive Differen- tial mode with Cable Loss @ 772 KHz Receiver Sensitivity of Receive Single Ended mode with Cable Loss @ 772 KHz Signal to Noise Interference Margin Analog LOS ...
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IDT82P2821 8.8 E1 TRANSMITTER ELECTRICAL CHARACTERISTICS Parameter Output Pulse Amplitude: E1, 75 Ω load E1, 120 Ω load Zero (Space) Level: E1, 75 Ω load E1, 120 Ω load Transmit Amplitude Variation with Supply Difference between Pulse Sequences for 17 ...
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IDT82P2821 8.9 T1/J1 TRANSMITTER ELECTRICAL CHARACTERISTICS Parameter Output Pulse Amplitude Zero (Space) Level Transmit Amplitude Variation with Supply Difference between Pulse Sequences for 17 consecutive pulses (T1.102) Output Pulse Width at 50% of Nominal Amplitude Pulse Width Variation at the ...
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IDT82P2821 8.10 TRANSMITTER AND RECEIVER TIMING CHARACTERISTICS Symbol MCLK Frequency: E1 T1/J1 MCLK Tolerance MCLK Duty Cycle Transmit Path TCLK Frequency: E1 T1/J1 TCLK Tolerance TCLK Duty Cycle t1 Transmit Data Setup Time t2 Transmit Data Hold Time Delay Time ...
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IDT82P2821 TCLKn TDn/TDPn TDNn/TMFn RCLK RDn/RDPn (RCK_ES = 0) RDNn/RMFn RDn/RDPn (RCK_ES = 1) RDNn/RMFn Physical And Electrical Specifications 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT t1 Figure-51 Transmit Clock Timing Diagram Figure-52 Receive ...
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IDT82P2821 8.11 CLKE1 TIMING CHARACTERISTICS Symbol CLKE1 outputs 2.048 MHz clock t1 CLKE1 Pulse Width t2 CLKE1 Pulse Width High Time t3 CLKE1 Pulse Width Low Time t4 LLOS Data Setup Time t5 LLOS Data Hold Time CLKE1 outputs 8kHz ...
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IDT82P2821 8.12 JITTER ATTENUATION CHARACTERISTICS Parameter Jitter Transfer Function Corner (-3 dB) Frequency: E1, 32/64/128-bit FIFO T1/J1, 32/64/128-bit FIFO Jitter Attenuator: E1 (G.736) T1/J1 (AT&T pub.62411) Jitter Attenuator Latency Delay: 32-bit FIFO 64-bit FIFO 128-bit FIFO Input Jitter Tolerance before ...
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IDT82P2821 Physical And Electrical Specifications 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Figure-54 E1 Jitter Tolerance Performance Figure-55 T1/J1 Jitter Tolerance Performance 134 February 6, 2009 ...
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IDT82P2821 Physical And Electrical Specifications 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT Figure-56 E1 Jitter Transfer Performance Figure-57 T1/J1 Jitter Transfer Performance 135 February 6, 2009 ...
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IDT82P2821 8.13 MICROPROCESSOR INTERFACE TIMING 8.13.1 SERIAL MICROPROCESSOR INTERFACE A falling transition on CS indicates the start of a read/write operation, and a rising transition indicates the end of the operation. After CS is set to low, a 5-bit instruction ...
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IDT82P2821 Symbol f SCLK Frequency OP t Minimum CS High Time CSH t CS Setup Time CSS t CS Hold Time CSD t Clock Disable Time CLD t Clock High Time CLH t Clock Low Time CLL t Data Setup ...
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IDT82P2821 8.13.2 PARALLEL MOTOROLA NON-MULTIPLEXED MICROPROCESSOR INTERFACE 8.13.2.1Read Cycle Specification Symbol t Address to valid read setup time SAR t Valid read signal width RSW t Address to valid read hold time HAR available time after valid ...
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IDT82P2821 8.13.2.2Write Cycle Specification Symbol t Address to valid write setup time SAW t Valid write signal width WSW t Address to valid write hold time HAW available time after valid write signal falling edge RWV t ...
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IDT82P2821 8.13.3 PARALLEL INTEL NON-MULTIPLEXED MICROPROCESSOR INTERFACE 8.13.3.1Read Cycle Specification Symbol Parameter t Address to valid read setup time SAR t Valid read signal width RSW t Address to valid read hold time HAR t Data propagation delay after valid ...
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IDT82P2821 8.13.3.2Write Cycle Specification Symbol t Address to valid write setup time SAW t Valid write signal width WSW t Address to valid write hold time HAW t Data available time before valid write signal rising edge DV t Valid ...
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IDT82P2821 8.13.4 PARALLEL MOTOROLA MULTIPLEXED MICROPROCESSOR INTERFACE 8.13.4.1Read Cycle Specification Symbol t Valid AS signal width ASW t Valid read signal width RSW t Valid falling edge delay after AS CSD available time after ...
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IDT82P2821 8.13.4.2Write Cycle Specification Symbol t Valid AS signal width ASW t Valid write signal width WSW valid hold time HCW available time after valid write signal falling edge RWV t R/ ...
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IDT82P2821 8.13.5 PARALLEL INTEL MULTIPLEXED MICROPROCESSOR INTERFACE 8.13.5.1Read Cycle Specification Symbol Parameter t Valid ALE signal width AEW t Valid read signal width RSW t Valid falling edge delay after ALE falling edge CSD t Valid address ...
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IDT82P2821 8.13.5.2Write Cycle Specification Symbol t Valid ALE signal width AEW t Valid write signal width WSW valid hold time HCW t Valid falling edge delay after ALE falling edge CSD t ...
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IDT82P2821 8.14 JTAG TIMING CHARACTERISTICS Symbol Parameter t1 TCK Period t2 TMS to TCK Setup Time; TDI to TCK Setup Time t3 TCK to TMS Hold Time; TCK to TDI Hold Time t4 TCK to TDO Delay Time TCK TMS ...
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AIS — AMI — ARB — B8ZS — BPV — CF — CV — DPLL — EXZ — FIFO — HDB3 — HPS — IB — LAIS — LBPV — LEXZ — LLOS — LOS — NRZ — PBX — ...
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IDT82P2821 SEXZ — SLOS — SONET — TEPBGA — TJA — TLOS — TOC — Glossary 21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT System Excessive Zeroes System LOS Synchronous Optical Network Thermally Enhanced Plastic Ball Grid Array Transmit Jitter Attenuator ...
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A Alarm Indication Signal (AIS) ............................................................. 47 B Bipolar Violation (BPV) ....................................................................... 43 C cable coaxial cable ........................................................... 29 twisted pair cable ................................................................. 29 clock input MCLK ......................................................................................... 66 XCLK .......................................................................................... 66 clock output CLKT1/CLKE1 ............................................................................ 61 REFA/REFB ............................................................................... 62 ...
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IDT82P2821 G.772 monitoring ........................................................................ 59 line monitor ................................................................................. 32 P pattern ARB ..................................................................................... 48 Inband Loopback (IB) .......................................................... 48 PRBS ................................................................................... 48 power down ................................................................................. 34 receiver ....................................................................................... 34 transmitter ................................................................................... 41 Protected Non-Intrusive Monitoring .................................................... 32 R receive sensitivity ...
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IDT82P2821 IDT82P2808A ORDERING INFORMATION XXXXXXX XX Device Type Package Data Sheet Document History 12/07/2005 Pages 10, 20, 23, 31, 44, 71, 72, 73, 120, 121, 126, 127, 136 01/11/2007 Page 129 02/06/2009 Pages 22, 61, 66 CORPORATE HEADQUARTERS 6024 Silver ...