IDT82P2821BHG IDT, Integrated Device Technology Inc, IDT82P2821BHG Datasheet - Page 75

• Manufacturer Part Number: IDT82P2821BHG
• Description: IC LINE INTERFACE UNIT 640-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2821BHG

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1703; 82P2821BHG

5.1.2
only the address of channel 1 is listed in the ‘Address (Hex)’ column of
the following table. For the addresses of the other channels, refer to the
description of each register.
Address
Channel Control
JA Configuration
Transmit Path Configuration
Receive Path Configuration
Diagnostics
Programming Information
IDT82P2821
(Hex)
00A
00B
00C
00D
00E
001
002
003
004
005
006
007
008
009
00F
010
Except for registers 7E5~7E9, which are channel 0 related registers,
PER-CHANNEL REGISTER
CHCF - Channel Configuration
Register
TJA - Transmit Jitter Attenuation
Configuration Register
RJA - Receive Jitter Attenuation
Configuration Register
TCF0 - Transmit Configuration
Register 0
TCF1 - Transmit Configuration
Register 1
PULS - Transmit Pulse Configu-
ration Register
SCAL - Amplitude Scaling Con-
trol Register
AWG0 - Arbitrary Waveform
Generation Control Register 0
AWG1 - Arbitrary Waveform
Generation Control Register 1
RCF0 - Receive Configuration
Register 0
RCF1 - Receive Configuration
Register 1
RCF2 - Receive Configuration
Register 2
LOS - LOS Configuration Regis-
ter
ERR - Error Detection & Inser-
tion Control Register
AISG - AIS Generation Control
Register
PG - Pattern Generation Control
Register
Register Name
RMF_DEF2 RMF_DEF1 RMF_DEF0
TMF_DEF2 TEM_DEF1 TMF_DEF0
EXZ_DEF
RCKH
Bit 7
LAC
-
-
-
-
-
-
-
-
-
-
BPV_INS
WDAT6
PG_CK
ALOS2
DONE
Bit 6
RHZ
OE
-
-
-
-
-
-
ERR_INS
PG_EN1
WDAT5
T_OFF
SCAL5
R_OFF
ALOS1
Bit 5
RW
-
-
-
-
-
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
75
CNT_SEL2 CNT_SEL1 CNT_SEL0
RJA_LIMT
TJA_LIMT
THZ_OC
RCK_ES
PG_EN0
TCK_ES
SAMP4
WDAT4
R120IN
SCAL4
ALOS0
Bit 4
-
-
-
-
ASAIS_SL
PG_POS
RJA_EN
TJA_EN
R_SING
RD_INV
TALOS1
T_SING
TD_INV
SAMP3
WDAT3
PULS3
SCAL3
Bit 3
OS
-
-
ASAIS_LLO
R_TERM2
T_TERM2
RJA_DP1
TJA_DP1
R_CODE
PAG_INV
T_CODE
TALOS0
SAMP2
WDAT2
PULS2
SCAL2
Bit 2
S
-
-
ALAIS_SLO
PRBG_SEL
R_TERM1
T_TERM1
RJA_DP0
TJA_DP0
CNT_MD
TDLOS1
CHRST
SAMP1
WDAT1
T_MD1
R_MD1
PULS1
SCAL1
Bit 1
MG1
S
1
CNT_STOP
ALAIS_LLO
PRBG_SEL
R_TERM0
T_TERM0
RJA_BW
TJA_BW
TDLOS0
SAMP0
WDAT0
R_MD0
T_MD0
PULS0
SCAL0
February 6, 2009
T1E1
Bit 0
MG0
S
0
Reference
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