IDT82P2821BHG IDT, Integrated Device Technology Inc, IDT82P2821BHG Datasheet - Page 41

• Manufacturer Part Number: IDT82P2821BHG
• Description: IC LINE INTERFACE UNIT 640-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82P2821BHG

• Function: Line Interface Unit (LIU)
• Interface: E1, J1, T1
• Number Of Circuits: 1
• Voltage - Supply: 1.8V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: *
• Includes: Defect and Alarm Detection, Driver Over-Current Detection and Protection, LLOS Detection, PRBSARB / IB Detection and Generation
• Number Of Transceivers: 1
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Power (watts): -
• Lead Free Status / RoHS Status: Compliant, Lead free / RoHS Compliant
• Other names: 800-1703; 82P2821BHG

3.3.7
sponding transmitter.
on the transmit line interface (including TTIPn and TRINGn) will be in
High-Z state. The input on the transmit system interface (including TDn,
TDPn, TDNn and TCLK) is ignored. The output on the transmit system
interface (i.e. TMFn) will be in High-Z state.
transmitter to achieve steady state, i.e., return to the previous configura-
tion and performance.
Functional Description
IDT82P2821
Set the T_OFF bit (b5, TCF0,...) to ‘1’ will power down the corre-
In this way, the corresponding transmit circuit is turned off. The pins
After clearing the T_OFF bit (b5, TCF0,...), it will take 1 ms for the
TRANSMITTER POWER DOWN
21(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
41
3.3.8
channel basis.
state globally:
state on a per-channel basis:
TTIPn and TRINGn can be set to High-Z state globally or on a per-
The following three conditions will set TTIPn and TRINGn to High-Z
• Connecting the OE pin to low;
• Loss of MCLK (i.e., no transition on MCLK for more than 1 ms);
• Power on reset, hardware reset by pulling RST to low for more
The following six conditions will set TTIPn and TRINGn to High-Z
• Writing ‘0’ to the OE bit (b6, TCF0,...);
• Loss of TCLKn in Transmit Single Rail NRZ Format mode or
• Transmitter power down;
• Per-channel software reset by writing ‘1’ to the CHRST bit (b1,
• Setting the THZ_OC bit (b4, TCF0,...) to ‘1’ when transmit driver
1. XCLK is derived from MCLK. It is 1.544 MHz in T1/J1 mode or 2.048 MHz
than 2 µs or global software reset by writing the RST register.
Transmit Dual Rail NRZ Format mode (i.e., no transition on TCLKn
for more than 64 XCLK
Remote Loopback or transmit internal pattern with XCLK;
CHCF,...);
over-current is detected.
in E1 mode.
OUTPUT HIGH-Z ON TTIP AND TRING
1
cycles) except that the channel is in
February 6, 2009