FM24C08 Fairchild Semiconductor, FM24C08 Datasheet

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FM24C08

Manufacturer Part Number
FM24C08
Description
Manufacturer
Fairchild Semiconductor
Datasheet

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© 2000 Fairchild Semiconductor International
FM24C08U/09U Rev. A.3
The FM24C08U/09U devices are 8192 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol. They are designed to
minimize device pin count and simplify PC board layout require-
ments.
The upper half (upper 4Kbit) of the memory of the FM24C09U can
be write protected by connecting the WP pin to V
memory then becomes unalterable unless WP is switched to V
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the FM24C32 or FM24C65 datasheets for more informa-
tion.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
SDA
SCL
V CC
V SS
WP
A2
START
SLAVE ADDRESS
LOGIC
STOP
COMPARATOR
REGISTER &
CC
. This section of
R/W
ADDRESS
COUNTER
WORD
CONTROL
D IN
LOGIC
SS
.
I Extended operating voltage 2.7V – 5.5V
I 400 KHz clock frequency (F) at 2.7V - 5.5V
I 200µA active current typical
I IIC compatible interface
I Sixteen byte page write mode
I Self timed write cycle
I Hardware Write Protect for upper half (FM24C09U only)
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I Available in three temperature ranges
XDEC
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
– Provides bi-directional data transfer protocol
– Minimizes total write time per byte
Typical write cycle time of 6ms
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
CK
TIMING &CONTROL
H.V. GENERATION
DATA REGISTER
E 2 PROM
ARRAY
YDEC
D OUT
www.fairchildsemi.com
August 2000

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FM24C08 Summary of contents

Page 1

... The FM24C08U/09U devices are 8192 bits of CMOS non-volatile electrically erasable memory. These devices conform to all speci- fications in the Standard IIC 2-wire protocol. They are designed to minimize device pin count and simplify PC board layout require- ments. The upper half (upper 4Kbit) of the memory of the FM24C09U can ...

Page 2

... NC No Connection Pins designated as "NC" are typically unbonded pins. However some of them are bonded for special testing purposes. Hence if a signal is applied to these pins, care should be taken that the voltage applied on these pins does not exceed the V FM24C08U/09U Rev. A ...

Page 3

... FM24C08U/09U Rev. A XXX Letter Description N 8-pin DIP M8 8-pin SOIC MT8 8-pin TSSOP Blank 0 to 70°C V -40 to +125°C E -40 to +85°C Blank 4.5V to 5.5V L 2.7V to 5.5V LZ 2.7V to 5.5V and <1µA Standby Current Blank 100KHz F 400KHz U Ultralite CS100UL with Write Protect ...

Page 4

... A This parameter is periodically sampled and not 100% tested. The "L" and "LZ" versions can be operated in the 2.7V to 5.5V V FM24C08U/09U Rev. A.3 Ambient Operating Temperature –65°C to +150°C FM24C08U/09U FM24C08UE/09UE – ...

Page 5

... During the write cycle, the WR FM24C08U/09U bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Refer "Write Cycle Timing" diagram. ...

Page 6

... It is recommended that the total line capacitance be less than 400pF SDA SCL V CC 24C02/ FM24C02U/03U Yes FM24C04U/05U No FM24C08U/09U No FM24C16U/17U No FM24C08U/09U Rev. A.3 ACK t WR STOP CONDITION Slave Master Slave Transmitter/ Transmitter Receiver Receiver 24C02/03 24C04/ ...

Page 7

... Last bit of the Slave Address indicates if the intended access is Read or Write. If the bit is "1," then the access is Read, whereas if the bit is "0," then the access is Write. FM24C08U/09U Rev. A.3 Acknowledge is an active LOW pulse on the SDA line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data ...

Page 8

... All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL is HIGH. The stop condition is also used by the FM24C08U/09U to place the device in the standby power mode, except when a Write operation is being executed, in which case a second stop condition is required ...

Page 9

... SCL SDA SCL SDA START CONDITION SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START CONDITION FM24C08U/09U Rev. A.3 DATA STABLE DATA CHANGE CONDITION STOP ACKNOWLEDGE PULSE www.fairchildsemi.com ...

Page 10

... FM24C08U/09U will respond with an acknowledge after the receipt of each subsequent eight bit byte. In the read mode the FM24C08U/09U slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowl- edge acknowledge is detected, FM24C08U/09U will continue to transmit data ...

Page 11

... The master then terminates the transfer by generating a stop condition at which time the FM24C08U/ 09U begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress, the FM24C08U/09U inputs ...

Page 12

... R/W bit set to one. This will be followed by an acknowl- edge from the FM24C08U/09U and then by the eight bit word. The master will not acknowledge the transfer but does generate the stop condition, and therefore the FM24C08U/09U discontinues transmission ...

Page 13

... Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference JEDEC registration MO153. Variation AA. Dated 7/93 FM24C08U/09U Rev. A.3 0.228 - 0.244 (5.791 - 6.198) Lead #1 IDENT 0.053 - 0.069 (1.346 - 1.753) 8¡ Max, Typ. All leads 0.014 0.016 - 0.050 (0.356) (0.406 - 1.270) ...

Page 14

... English Français Italiano Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. FM24C08U/09U Rev. A.3 0.373 - 0.400 (9.474 - 10.16) 0.090 (2.286) ...

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