74VHC74MSCX Fairchild Semiconductor, 74VHC74MSCX Datasheet

74VHC74MSCX

Manufacturer Part Number

74VHC74MSCX

Description

Dual D-Type Flip-Flop with Preset and Clear

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VHC74MSCX.pdf (6 pages)

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74VHC74M

74VHC74SJ

74VHC74MTC

74VHC74N

74VHC74

Dual D-Type Flip-Flop with Preset and Clear

General Description

The VHC74 is an advanced high speed CMOS Dual D-

Type Flip-Flop fabricated with silicon gate CMOS technol-

ogy. It achieves the high speed operation similar to equiva-

lent Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The signal level applied to the D input is

transferred to the Q output during the positive going transi-

tion of the CK pulse. CLR and PR are independent of the

CK and are accomplished by setting the appropriate input

LOW.

An input protection circuit ensures that 0V to 7V can be

applied to the input pins without regard to the supply volt-

Ordering Code:

Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Symbol

Pin Descriptions

Order Number

CLR

, D

, Q

, CK

, PR

, CLR

Pin Names

, Q

Package Number

MTC14

IEEE/IEC

M14A

M14D

N14A

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Preset Inputs

Output

Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

DS011505.prf

age. This device can be used to interface 5V to 3V systems

and two supply systems such as battery backup. This cir-

cuit prevents device destruction due to mismatched supply

and input voltages.

Features

Connection Diagram

Truth Table

Note 1: This configuration is nonstable; that is, it will not persist when pre-

set and clear inputs return to their inactive (HIGH) state.

CLR PR

High Speed: f

High noise immunity: V

Power down protection is provided on all inputs

Low power dissipation: I

Pin and function compatible with 74HC74

Package Description

Inputs

MAX

170 MHz (typ) at T

H (Note 1) H (Note 1)

NIH

October 1992

Revised March 1999

2 A (max) at T

Outputs

NIL

28% V

www.fairchildsemi.com

25 C

(min)

Clear

Preset

No Change

Function

25 C

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74VHC74MSCX Summary of contents

Page 1

... Output © 1999 Fairchild Semiconductor Corporation age. This device can be used to interface systems and two supply systems such as battery backup. This cir- cuit prevents device destruction due to mismatched supply and input voltages. Features High Speed: f 170 MHz (typ ...

Page 2

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( OUT Input Diode Current ( Output Diode Current ( Output Current (I ) ...

Page 3

AC Electrical Characteristics V CC Symbol Parameter (V) f Maximum Clock 3.3 0.3 MAX Frequency 5.0 0.5 t Propagation Delay 3.3 0.3 PLH t Time (CK-Q, Q) PHL 5.0 0.5 t Propagation Delay Time 3.3 0.3 PLH t (CLR, PR ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide www.fairchildsemi.com Package Number M14A Package Number M14D 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN ...

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