NM34C02M8X Fairchild Semiconductor, NM34C02M8X Datasheet

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NM34C02M8X

Manufacturer Part Number
NM34C02M8X
Description
2K-Bit with Standard 2-Wire Bus Interface Designed w/Permanent Write-Protection for First 128 Bytes for Serial Detect Application on Memory Modules
Manufacturer
Fairchild Semiconductor
Datasheet
© 1999 Fairchild Semiconductor Corporation
NM34C02 Rev. D.2
NM34C02
2K-Bit Standard 2-Wire Bus Interface
Designed with Permanent Write-Protection for First 128 Bytes for Serial Presence
Detect Application on Memory Modules
General Description
The NM34C02 is 2048 bits of CMOS non-volatile electrically
erasable memory. It is designed to support Serial Presence
Detect circuitry in memory modules. This communications proto-
col uses CLOCK (SCL) and DATA I/O (SDA) lines to synchro-
nously clock data between the master (for example a micropro-
cessor) and the slave EEPROM device(s).
The contents of the non-volatile memory allows the CPU to
determine the capacity of the module and the electrical character-
istics of the memory devices it contains. This will enable "plug and
play" capability as the module is read and PC main memory
resources utilized through the memory controller.
The first 128 bytes of the memory of the NM34C02 can be
permanently Write Protected by writing to the "WRITE PROTECT"
Register. Write Protect implementation details are described
under the section titled Addressing the WP Register.
The NM34C02 is available in a JEDEC standard TSSOP package
for low profile memory modules for systems requiring efficient
space utilization such as in a notebook computer. Two options are
available: L - Low Voltage and LZ - Low Power, allowing the part
to be used in systems where battery life is of primary importance.
Block Diagram
SDA
SCL
V CC
V SS
A2
A1
A0
Write Protect
SLAVE ADDRESS
START
LOGIC
STOP
COMPARATOR
Register
REGISTER &
Device Address Bits
R/W
LOAD
ADDRESS
COUNTER
WORD
CONTROL
D IN
LOGIC
INC
1
START CYCLE
Features
Extended Operating Voltage: 2.7V-5.5V
Write-Protection for first 128 bytes
200 A active current typical
– 10 A standby current typical
– 1.0 A standby current typical (L)
– 0.1 A standby current typical (LZ)
IIC compatible interface
– Provides bidirectional data transfer protocol
Sixteen byte page write mode
– Minimizes total write time per byte
Self timed write cycle
- Typical write cycle time of 6ms
Endurance: 1,000,000 data changes
Data retention greater than 40 years
Packages available: 8-pin TSSOP and 8-pin SO
XDEC
4
CK
0/1/2/3
4
16
TIMING &CONTROL
H.V. GENERATION
DATA REGISTER
16 x 16 x 8
E 2 PROM
ARRAY
YDEC
16
8
D OUT
www.fairchildsemi.com
March 1999
DS012821-1

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NM34C02M8X Summary of contents

Page 1

... Block Diagram SDA SCL © 1999 Fairchild Semiconductor Corporation NM34C02 Rev. D.2 Features Extended Operating Voltage: 2.7V-5.5V Write-Protection for first 128 bytes 200 A active current typical – standby current typical – 1.0 A standby current typical (L) – 0.1 A standby current typical (LZ) IIC compatible interface – ...

Page 2

Connection Diagram Ordering Information NM34C02 NM34C02 Rev. D.2 SO (M8) and TSSOP (MT8) Package NM34C02 SCL SDA DS012821-2 Top View See ...

Page 3

Product Specifications Absolute Maximum Ratings Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating Standard V (4.5V to 5.5V) DC Electrical Characteristics CC Symbol Parameter I Active Power Supply Current ...

Page 4

AC Conditions of Test Input Pulse Levels V CC Input Rise and Fall Times 10 ns Input & Output Timing Levels V CC Output Load 1 TTL Gate and C Read and Write Cycle Limits (Standard and Low V Symbol ...

Page 5

Bus Timing SCL t SU:STA SDA IN SDA OUT Background Information (IIC Bus) As mentioned, the IIC bus allows synchronous bidirectional com- munication between Transmitter/Receiver using the SCL (clock) and SDA (Data I/O) lines. All communication must be started with ...

Page 6

Device NM34C02 Pin Descriptions Serial Clock (SCL) The SCL input is used to clock all data into and out of the device. Serial Data (SDA) SDA is a bidirectional pin used to transfer data into and out of the device. ...

Page 7

Write Cycle Timing SCL SDA WORD n SCL SDA SCL CONDITION SDA SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER Acknowledge Responses from Receiver (Figure 3). Device Addressing Following a start condition the master must output the ...

Page 8

Device Addressing (Continued) Device Type Device Identifier Address NM34C02 Slave Addresses (Figure 4). Refer to the following table for Slave Address string details: Device Page Blocks NM34C02 ...

Page 9

Write Protect Scheme (Continued) Bus Activity: Master R SDA Line S T SLAVE A Bus Activity: ADDRESS R Master T SDA Line Bus Activity: Master SDA Line Bus Activity: Read Operations Read operations are initiated in the same manner as ...

Page 10

Read Operations (Continued) operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. After the entire memory has been read, the counter 'rolls over' and the NM34C02 continues to output data for ...

Page 11

Physical Dimensions inches (millimeters) unless otherwise noted 0.150 - 0.157 (3.810 - 3.988) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.04 0.0075 - 0.0098 (0.102) (0.190 - 0.249) All lead tips Typ. All Leads 8-Pin Molded Small Outline Package ...

Page 12

... Life Support Policy Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support ...

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