NM24C16M8X Fairchild Semiconductor, NM24C16M8X Datasheet

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NM24C16M8X

Manufacturer Part Number
NM24C16M8X
Description
16K-Bit Standard 2-Wire Bus Interface Serial EEPROM [Not recommended for new designs]
Manufacturer
Fairchild Semiconductor
Datasheet
© 1998 Fairchild Semiconductor Corporation
NM24C16/17 Rev. G
The NM24C16/17 devices are 16,384 bits of CMOS non-volatile
electrically erasable memory. These devices conform to all speci-
fications in the Standard IIC 2-wire protocol and are designed to
minimize device pin count, and simplify PC board layout require-
ments.
The upper half (upper 8Kbit) of the memory of the NM24C17 can be
write protected by connecting the WP pin to V
memory then becomes unalterable unless WP is switched to V
This communications protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the master
(for example a microprocessor) and the slave EEPROM device(s).
The Standard IIC protocol allows for a maximum of 16K of
EEPROM memory which is supported by the Fairchild family in
2K, 4K, 8K, and 16K devices, allowing the user to configure the
memory as the application requires with any combination of
EEPROMs. In order to implement higher EEPROM memory
densities on the IIC bus, the Extended IIC protocol must be used.
(Refer to the NM24C32 or NM24C65 datasheets for more infor-
mation.)
Fairchild EEPROMs are designed and tested for applications requir-
ing high endurance, high reliability and low power consumption.
SDA
SCL
V CC
V SS
WP
START
SLAVE ADDRESS
LOGIC
STOP
REGISTER
CC
. This section of
R/W
ADDRESS
COUNTER
WORD
CONTROL
D IN
LOGIC
SS
.
I Extended operating voltage 2.7V – 5.5V
I 400 KHz clock frequency (F) at 2.7V - 5.5V
I 200µA active current typical
I IIC compatible interface
I Schmitt trigger inputs
I Sixteen byte page write mode
I Self timed write cycle
I Hardware Write Protect for upper half (NM24C17 only)
I Endurance: 1,000,000 data changes
I Data retention greater than 40 years
I Packages available: 8-pin DIP, 8-pin SO, and 8-pin TSSOP
I Available in three temperature ranges
XDEC
10µA standby current typical
1µA standby current typical (L)
0.1µA standby current typical (LZ)
– Provides bi-directional data transfer protocol
– Minimizes total write time per byte
Typical write cycle time of 6ms
- Commercial: 0° to +70°C
- Extended (E): -40° to +85C
- Automotive (V): -40° to +125°C
CK
TIMING &CONTROL
H.V. GENERATION
DATA REGISTER
E 2 PROM
ARRAY
YDEC
D OUT
February 2000
www.fairchildsemi.com
DS500072-1

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NM24C16M8X Summary of contents

Page 1

... WP START SDA STOP LOGIC SLAVE ADDRESS SCL © 1998 Fairchild Semiconductor Corporation NM24C16/17 Rev Extended operating voltage 2.7V – 5.5V I 400 KHz clock frequency (F) at 2.7V - 5.5V I 200µA active current typical 10µA standby current typical 1µA standby current typical (L) 0.1µA standby current typical (LZ) ...

Page 2

NM24C16 Ground SS SDA Serial Data I/O SCL Serial Clock Input NC No Connection V Power Supply NM24C17 ...

Page 3

NM24C16/17 Rev XXX Letter Description N 8-pin DIP M8 8-pin SOIC MT8 8-pin TSSOP None 0 to 70°C V -40 to +125°C E -40 to +85°C Blank 4.5V to 5.5V L 2.7V ...

Page 4

Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 seconds) ESD Rating I Active Power Supply Current f CCA I Standby Current SB I Input Leakage Current LI I Output Leakage Current LO ...

Page 5

Input Pulse Levels V CC Input Rise and Fall Times 10 ns Input & Output Timing Levels V CC Output Load 1 TTL Gate and C f SCL Clock Frequency SCL T Noise Suppression Time Constant at I SCL, SDA ...

Page 6

SCL SDA 8th BIT WORD n The write cycle time ( the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. WR SDA SCL Master Transmitter/ Receiver Due to ...

Page 7

IIC bus allows synchronous bi-directional communication be- tween a TRANSMITTER and a RECEIVER using a Clock signal (SCL) and a Data signal (SDA). Additionally there are up to three Address signals (A2, A1 and A0) which collectively serve as "chip ...

Page 8

The SCL input is used to clock all data into and out of the device. SDA is a bi-directional pin used to transfer data into and out of the device open drain output and may be wire–ORed ...

Page 9

SCL SDA SCL SDA START CONDITION SCL FROM MASTER DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER START CONDITION NM24C16/17 Rev. G DATA STABLE DATA CHANGE CONDITION DS500072-11 STOP DS500072- ACKNOWLEDGE PULSE DS500072-13 ...

Page 10

The NM24C16/17 device will always respond with an acknowl- edge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the NM24C16/17 will respond with an acknowledge after the ...

Page 11

For a write operation a second address field is required which is a word address that is comprised of eight bits and provides access to any one of the 256 bytes in the selected page of memory. Upon receipt of ...

Page 12

Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. There are three basic read operations: current address read, random read, and sequential ...

Page 13

All lead tips Typ. All Leads 0.114 - 0.122 (2.90 - 3.10) 8 ...

Page 14

... Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support ...

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