DM74LS74ASJ Fairchild Semiconductor, DM74LS74ASJ Datasheet

DM74LS74ASJ

Manufacturer Part Number

DM74LS74ASJ

Description

Dual Positive-Edge-Triggered D Flip-Flop with Preset Clear and Complementrary Outputs

Manufacturer

Fairchild Semiconductor

Datasheet

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DM74LS74AM

DM74LS85ASJ

DM74LS74AN

DM74LS74A

Dual Positive-Edge-Triggered D Flip-Flops with

Preset, Clear and Complementary Outputs

General Description

This device contains two independent positive-edge-trig-

gered D flip-flops with complementary outputs. The infor-

mation on the D input is accepted by the flip-flops on the

positive going edge of the clock pulse. The triggering

occurs at a voltage level and is not directly related to the

transition time of the rising edge of the clock. The data on

the D input may be changed while the clock is LOW or

HIGH without affecting the outputs as long as the data

setup and hold times are not violated. A low logic level on

the preset or clear inputs will set or reset the outputs

regardless of the logic levels of the other inputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Order Number

Package Number

M14A

M14D

N14A

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

DS006373

Function Table

established.

Note 1: This configuration is nonstable; that is, it will not persist when either

the preset and/or clear inputs return to their inactive (HIGH) level.

LOW Logic Level

Positive-going Transition

Either LOW or HIGH Logic Level

HIGH Logic Level

The output logic level of Q before the indicated input conditions were

Package Description

CLR

Inputs

CLK

August 1986

Revised March 2000

H (Note 1) H (Note 1)

www.fairchildsemi.com

Outputs

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DM74LS74ASJ Summary of contents

Page 1

... DM74LS74AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram © 2000 Fairchild Semiconductor Corporation Package Description Function Table Inputs PR CLR ...

Page 2

Absolute Maximum Ratings Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range Recommended Operating Conditions Symbol Parameter V Supply Voltage CC V HIGH Level Input Voltage IH V LOW Level Input Voltage IL I HIGH Level Output ...

Page 3

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter V Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage V ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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