AD8331ARQ-REEL Analog Devices Inc, AD8331ARQ-REEL Datasheet - Page 32

• Manufacturer Part Number: AD8331ARQ-REEL
• Description: IC VGA SINGLE W/PREAMP 20-SSOP
• Manufacturer: Analog Devices Inc
• Series: X-AMP®r
• Type: Variable Gain Amplifierr

Specifications of AD8331ARQ-REEL

• Rohs Status: RoHS non-compliant
• Design Resources: Interfacing the High Frequency AD8331 to AD9215 (CN0096)
• Applications: Signal Processing
• Mounting Type: Surface Mount
• Package / Case: 20-QSOP
• For Use With: AD8331-EVALZ - BOARD EVAL FOR AD8331

AD8331/AD8332/AD8334
with gains less than 40 dB. The exact values of these components
can be selected empirically.
An antialiasing noise filter is typically used with an ADC. Filter
requirements are application dependent.
When the ADC resides on a separate board, the majority of
filter components should be placed nearby to suppress noise
picked up between boards and to mitigate charge kickback from
the ADC inputs. Any series resistance beyond that required for
output stability should be placed on the ADC board. Figure 85
shows a second-order, low-pass filter with a bandwidth of 20 MHz.
The capacitor is chosen in conjunction with the 10 pF input
capacitance of the ADC.
DRIVING ADCs
The output drive accommodates a wide range of ADCs. The
noise floor requirements of the VGA depend on a number of
application factors, including bit resolution, sampling rate, full-
scale voltage, and the bandwidth of the noise/antialias filter. The
output noise floor and gain range can be adjusted by selecting
HI or LO gain mode.
The relative noise and distortion performance of the two gain
modes can be compared in Figure 25 and Figure 31 through
Figure 41. The 48 nV/√Hz noise floor of the LO gain mode is
suited to converters with higher sampling rates or resolutions
(such as 12 bits). Both gain modes can accommodate ADC full-
scale voltages as high as 4 V p-p. Because distortion performance
remains favorable for output voltages as high as 4 V p-p (see
Figure 36), it is possible to lower the output-referred noise even
further by using a resistive attenuator (or transformer) at the
output. The circuit in Figure 86 has an output full-scale range of
2 V p-p, a gain range of −10.5 dB to +37.5 dB, and an output
noise floor of 24 nV/√Hz, making it suitable for some 14-bit
ADC applications.
OVERLOAD
These devices respond gracefully to large signals that overload
its input stage and to normal signals that overload the VGA
when the gain is set unexpectedly high. Each stage is designed
for clean-limited overload waveforms and fast recovery when
gain setting or input amplitude is reduced.
84.5Ω
84.5Ω
Figure 86. Adjusting the Noise Floor for 14-Bit ADCs
Figure 85. 20 MHz Second-Order, Low-Pass Filter
0.1µF
0.1µF
VOH
VOL
4V p-p DIFF,
48nV/ Hz
BACKPLANE
OPTIONAL
187Ω
187Ω
2:1
2V p-p DIFF,
1.5µH
1.5µH
24nV/ Hz
374Ω
158Ω
158Ω
LPF
18pF
AD6644
ADC
ADC
Rev. G | Page 32 of 56
Signals larger than ±275 mV at the LNA input are clipped to
5 V p-p differential prior to the input of the VGA. Figure 48
shows the response to a 1 V p-p input burst. The symmetric
overload waveform is important for applications, such as CW
Doppler ultrasound, where the spectrum of the LNA outputs
during overload is critical. The input stage is also designed to
accommodate signals as high as ±2.5 V without triggering the
slow-settling ESD input protection diodes.
Both stages of the VGA are susceptible to overload. Post-
amplifier limiting is more common and results in the clean-
limited output characteristics found in Figure 49. Recovery is fast in
all cases. The graph in Figure 87 summarizes the combinations of
input signal and gain that lead to the different types of overload.
The clamp interface mentioned in the Output Clamping section
controls the maximum output swing of the postamp and its
overload response. When the clamp feature is not used, the
output level defaults to approximately 4.5 V p-p differential
centered at 2.5 V common mode. When other common-mode
levels are set through the VCM pin, the value of R
selected for graceful overload. A value of 8.3 kΩ or less is
recommended for 1.5 V or 3.5 V common-mode levels (7.2 kΩ
for HI gain mode). This limits the output swing to just above
2 V p-p differential.
OPTIONAL INPUT OVERLOAD PROTECTION
Applications in which high transients are applied to the LNA
input can benefit from the use of clamp diodes. A pair of back-
to-back Schottky diodes can reduce these transients to manageable
levels. Figure 88 illustrates how such a diode protection scheme
can be connected.
43.5
–4.5
1m
OVERLOAD
POSTAMP
INPUT AMPLITUDE (V)
OVERLOAD
SCHOTTKY
LO GAIN
OPTIONAL
15mV
2
MODE
10m
CLAMP
BAS40-04
Figure 87. Overload Gain and Signal Conditions
3
OVERLOAD
25mV
1
X-AMP
Figure 88. Input Overload Clamping
FB
0.1
0.275
0.1µF
C
1
R
29dB
24.5dB
SH
SH
56.5
7.5
C
R
IZ
1m
IZ
OVERLOAD
POSTAMP
4mV
INPUT AMPLITUDE (V)
10m
2
3
4
HI GAIN
MODE
INH
VPSL
LON
OVERLOAD
25mV
X-AMP
CLMP
0.1
COMM
ENBL
0.275
should be
20
19
1
41dB
24.5dB