AT89C51RD2 Atmel Corporation, AT89C51RD2 Datasheet - Page 13
AT89C51RD2
Manufacturer Part Number
AT89C51RD2
Description
Manufacturer
Atmel Corporation
Specifications of AT89C51RD2
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
60 MHz
Cpu
8051-12C
Max I/o Pins
32
Spi
1
Uart
1
Sram (kbytes)
2
Self Program Memory
API
Operating Voltage (vcc)
2.7 to 5.5
Timers
4
Isp
UART
Watchdog
Yes
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Table 4-1.
4235K–8051–05/08
ALE/PRO
G
PSEN
EA
Mnemonic
Pin Description (Continued)
PLCC44 VQFP44
33
32
35
27
26
29
Pin Number
PLCC68
68
67
2
VQFP64
56
55
58
Type
O (I)
O
I
Name and Function
Address Latch Enable/Program Pulse: Output pulse for latching the
low byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking. Note
that one ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With
this bit set, ALE will be inactive during internal fetches.
Program Strobe ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH. If security level 1 is programmed, EA will be internally latched on
Reset.
AT89C51RD2/ED2
13