AT89C51RD2 Atmel Corporation, AT89C51RD2 Datasheet - Page 67

• Manufacturer Part Number: AT89C51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 2
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

Figure 16-4. Data Transmission Format (CPHA = 0)
Figure 16-5. Data Transmission Format (CPHA = 1)
Figure 16-6. CPHA/SS Timing
16.3.3
4235K–8051–05/08
Error Conditions
MOSI (from Master)
SCK Cycle Number
MISO (from Slave)
MOSI (from Master)
SCK (CPOL = 0)
SCK (CPOL = 1)
MISO (from Slave)
SCK Cycle Number
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
Capture Point
SPEN (Internal)
SS (to Slave)
Capture Point
SS (to Slave)
As shown in
must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to
start the transmission. The SS pin must be toggled high and then low between each Byte trans-
mitted (Figure 16-6).
Figure 16-5
driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first SCK edge as a
start transmission signal. The SS pin can remain low between transmissions
format may be preferred in systems having only one Master and only one Slave driving the
MISO data line.
The following flags in the SPSTA signal SPI error conditions:
MISO/MOSI
(CPHA = 0)
(CPHA = 1)
Master SS
Slave SS
Slave SS
shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins
Figure
MSB
MSB
MSB
1
MSB
1
16-4, the first SCK edge is the MSB capture strobe. Therefore, the Slave
2
bit6
bit6
2
bit6
Byte 1
bit6
3
bit5
bit5
3
bit5
bit5
bit4
4
bit4
bit4
4
bit4
Byte 2
bit3
bit3
5
bit3
bit3
5
6
bit2
bit2
6
bit2
bit2
Byte 3
7
bit1
bit1
7
bit1
bit1
AT89C51RD2/ED2
LSB
8
LSB
LSB
8
LSB
(Figure
16-6). This
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