AT89C51RD2 Atmel Corporation, AT89C51RD2 Datasheet - Page 35

• Manufacturer Part Number: AT89C51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 2
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

13. Programmable Counter Array (PCA)
4235K–8051–05/08
The PCA provides more timing capabilities with less CPU intervention than the standard
timer/counters. Its advantages include reduced software overhead and improved accuracy. The
PCA consists of a dedicated timer/counter which serves as the time base for an array of five
compare/capture modules. Its clock input can be programmed to count any one of the following
signals:
Each compare/capture module can be programmed in any one of the following modes:
Module 4 can also be programmed as a watchdog timer (see Section "PCA Watchdog Timer",
page 46).
When the compare/capture modules are programmed in the capture mode, software timer, or
high speed output mode, an interrupt can be generated when the module executes its function.
All five modules plus the PCA timer overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins
are listed below. If one or several bits in the port are not used for the PCA, they can still be used
for standard I/O.
The PCA timer is a common time base for all five modules (see Figure 13-1). The timer count
source is determined from the CPS1 and CPS0 bits in the CMOD register (Table 13-1) and can
be programmed to run at:
The CMOD register includes three additional bits associated with the PCA (See Figure 13-1 and
Table 13-1).
• Peripheral clock frequency (F
• Peripheral clock frequency (F
• Timer 0 overflow
• External input on ECI (P1.2)
• Rising and/or falling edge capture
• Software timer
• High-speed output
• Pulse width modulator
• 1/6 the
• 1/2 the
• The Timer 0 overflow
• The input on the ECI pin (P1.2)
• The CIDL bit which allows the PCA to stop during idle mode.
• The WDTE bit which enables or disables the watchdog function on module 4.
peripheral clock frequency (F
peripheral clock frequency (F
PCA Component
16-bit Module 0
16-bit Module 1
16-bit Module 2
16-bit Module 3
16-bit Counter
CLK PERIPH
CLK PERIPH
)
)
CLK PERIPH
CLK PERIPH
÷
÷
2
6
)
)
AT89C51RD2/ED2
External I/O Pin
P1.3/CEX0
P1.4/CEX1
P1.5/CEX2
P1.6/CEX3
P1.2/ECI
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