AT89C51RD2 Atmel Corporation, AT89C51RD2 Datasheet - Page 23

• Manufacturer Part Number: AT89C51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 2
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

9. Expanded RAM (XRAM)
Figure 9-1.
4235K–8051–05/08
0FFh or 6FFh
Internal and External Data Memory Address
00
The AT89C51RD2/ED2 provides additional on-chip random access memory (RAM) space for
increased data parameter handling and high level language usage.
AT89C51RD2/ED2 device haS expanded RAM in external data space configurable up to 1792
bytes (see
The AT89C51RD2/ED2 internal data memory is mapped into four separate segments.
The four segments are:
The lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128
bytes can be accessed by indirect addressing only. The Upper 128 bytes occupy the same
address space as the SFR. That means they have the same address, but are physically sepa-
rate from SFR space.
When an instruction accesses an internal location above address 7Fh, the CPU knows whether
the access is to the upper 128 bytes of data RAM or to SFR space by the addressing mode used
in the instruction.
1. The Lower 128 bytes of RAM (addresses 00h to 7Fh) are directly and indirectly
2. The Upper 128 bytes of RAM (addresses 80h to FFh) are indirectly addressable only.
3. The Special Function Registers, SFRs, (addresses 80h to FFh) are directly address-
4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the
• Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data,
• Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For
• The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and
accesses the SFR at location 0A0h (which is P2).
example: MOV @R0, # data where R0 contains 0A0h, accesses the data byte at address
0A0h, rather than P2 (whose address is 0A0h).
MOVX instructions. This part of memory which is physically located on-chip, logically
occupies the first bytes of external data memory. The bits XRS0 and XRS1 are used to hide a
XRAM
addressable.
able only.
EXTRAM bit cleared in the AUXR register (see Table 9-1).
Table
0FFh
9-1).
80h
7Fh
00
Indirect Accesses
Direct or Indirect
128 Bytes
128 Bytes
Accesses
Internal
Internal
Upper
Lower
RAM
RAM
0FFh
80h
Direct Accesses
Function
Register
Special
00FFh up to 06FFh
AT89C51RD2/ED2
0FFFFh
0000
External
Memory
Data
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