AT89C51RD2 Atmel Corporation, AT89C51RD2 Datasheet - Page 87

• Manufacturer Part Number: AT89C51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89C51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 60 MHz
• Cpu: 8051-12C
• Max I/o Pins: 32
• Spi: 1
• Uart: 1
• Sram (kbytes): 2
• Self Program Memory: API
• Operating Voltage (vcc): 2.7 to 5.5
• Timers: 4
• Isp: UART
• Watchdog: Yes

21. Power-off Flag
4235K–8051–05/08
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (Table 21-1). POF is set by hardware
when V
ing the user to determine the type of reset.
Table 21-1.
PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
Number
SMOD1
Bit
7
7
6
5
4
3
2
1
0
CC
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
Mnemonic
PCON Register
SMOD1
SMOD0
SMOD0
POF
GF1
GF0
IDL
Bit
PD
6
-
Description
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0
Cleared to select SM0 bit in SCON register.
Set to select FE bit in SCON register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Cleared by software to recognize the next reset type.
Set by hardware when V
software.
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
General-purpose Flag
Cleared by user for general-purpose usage.
Set by user for general-purpose usage.
Power-down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
Cleared by hardware when interrupt or reset occurs.
Set to enter idle mode.
5
-
POF
CC
4
switch-on. A warm start reset occurs while V
CC
rises from 0 to its nominal voltage. Can also be set by
GF1
3
AT89C51RD2/ED2
GF0
2
PD
1
CC
IDL
0
is still
87