AD9257 Analog Devices, AD9257 Datasheet - Page 30

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight bit
locations. The memory map is roughly divided into three
sections: the chip configuration registers (Address 0x00
to Address 0x02); the device index and transfer registers
(Address 0x05 and Address 0xFF); and the global ADC
functions registers, including setup, control, and test
(Address 0x08 to Address 0x109).
The memory map register table (see Table 17) lists the default
hexadecimal value for each hexadecimal address shown. The
column with the heading Bit 7 (MSB) is the start of the default
hexadecimal value given. For example, Address 0x05, the device
index register, has a hexadecimal default value of 0x3F. This
means that in Address 0x05, Bits[7:6] = 0, and the remaining
Bits[5:0] = 1. This setting is the default channel index setting.
The default value results in both ADC channels receiving the
next write command. For more information on this function
and others, see the
High Speed ADCs via SPI. This application note details the
functions controlled by Register 0x00 to Register 0xFF. The
remaining registers are documented in the Memory Map
Register Descriptions section.
Open Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location should be written with 0s. Writing to these
locations is required only when part of an address location is
open (for example, Address 0x05). If the entire address location
is open or not listed in Table 17 (for example, Address 0x13) this
address location should not be written.
AN-877
Application Note, Interfacing to
Rev. 0 | Page 30 of 40
Default Values
After the
default values. The default values for the registers are given in
Table 17, the memory map register table.
Logic Levels
An explanation of logic level terminology follows:
•
•
Channel-Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed differently for each channel. In
these cases, channel address locations are internally duplicated
for each channel. These registers and bits are designated in
Table 17 as local. These local registers and bits can be accessed
by setting the appropriate data channel bits (A, B, C, or D) and
the clock channel DCO/FCO bits (Bits[5:4]) in Register 0x05. If
all the bits are set, the subsequent write affects the registers of
all channels and the DCO/FCO clock channels. In a read cycle,
only one of the channels, A, B, C, or D, should be set to read
one of the four registers. If all the bits are set during a SPI read
cycle, the part returns the value for Channel A. Registers and
bits designated as global in Table 17 affect the entire part or the
channel features for which independent settings are not allowed
between channels. The settings in Register 0x05 do not affect
the global registers and bits.
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit. ”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit. ”
AD9257
is reset, critical registers are loaded with
Data Sheet