AD9257 Analog Devices, AD9257 Datasheet - Page 32

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
Reg.
Addr.
(Hex)
0x0B
0x0C
0x0D
0x10
0x14
0x15
0x16
0x18
Register Name
Clock divide
(global)
Enhancement
control
Test mode (local
except for PN
sequence resets)
Offset adjust (local)
Output mode
Output adjust
Output phase
V
REF
Bit 7
(MSB)
Open
Open
Open
Open
Open
Open
(affects user input test
User input test mode
11 = alternate once
10 = single once
Bits[3:0] = 1000)
01 = alternate
mode only,
00 = single
Bit 6
Open
Open
LVDS-ANSI/
LVDS-IEEE
option
0 = LVDS-
ANSI
1 = LVDS-
IEEE reduced
range link
(global);
(see Table 18)
Open
Open
(value is number of input clock cycles
Input clock phase adjust, Bits[6:4]
Offset adjust in LSBs from +127 to −128 (twos complement format)
of phase delay)
(see Table 19)
Bit 5
Open
Open
Reset PN
long gen
Open
Open
8-bit device offset adjustment, Bits[7:0] (local)
Output driver
termination,
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
00 = none
Bits[1:0]
Rev. 0 | Page 32 of 40
Bit 4
Open
Open
Reset
PN
short
gen
Open
Open
Bit 3
Open
Open
Open
Open
Open
Output clock phase adjust, Bits[3:0]
Output test mode, Bits[3:0] (local)
0100 = alternating checkerboard
(Setting = 0000 through 1011)
0111 = one/zero word toggle
1100 = mixed bit frequency
0000 = off (default)
0010 = positive FS
0011 = negative FS
0101 = PN 23 sequence
0110 = PN 9 sequence
1000 = user input
1010 = 1× sync
1011 = one bit high
Bit 2
Chop
mode
0 = off
1 = on
Output
invert
(local)
Open
0001 = midscale short
1001 = 1-/0-bit toggle
(see Table 20)
Clock divide ratio, Bits[2:0]
Internal V
digital scheme, Bits[2:0]
000 = 1.0 V p-p
011 = 1.6 V p-p
100 = 2.0 V p-p
000 = divide by 1
001 = divide by 2
010 = divide by 3
011 = divide by 4
100 = divide by 5
101 = divide by 6
110 = divide by 7
111 = divide by 8
001 = 1.14 V p-p
010 = 1.33 V p-p
Open
Bit 1
Open
Open
REF
adjustment
Bit 0 (LSB)
Open
Output
format
0 = offset
binary
1 = twos
comple-
ment
(global)
Output
drive
0 = 1×
drive
1 = 2×
drive
Default
Value
(Hex)
0x00
0x00
0x00
0x00
0x01
0x00
0x03
0x04
Data Sheet
Comments
The divide
ratio is the
value plus 1.
Enables/
disables chop
mode.
When set, the
test data is
placed on the
output pins in
place of
normal data.
Device offset
trim.
Configures the
outputs and
the format of
the data.
Determines
LVDS or
other output
properties.
On devices
that use global
clock divide,
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal
latching is
unaffected.
Selects and/or
adjusts the
V
REF
.