AD9257 Analog Devices, AD9257 Datasheet - Page 34

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

AD9257
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0xFF, see the
Interfacing to High Speed ADCs via SPI.
Device Index (Register 0x04 and Register 0x05)
There are certain features in the map that can be set
independently for each channel, whereas other features apply
globally to all channels (depending on context), regardless of
which are selected. The first four bits in Register 0x04 and
Register 0x05 can be used to select which individual data channels
are affected. The output clock channels can be selected in
Register 0x05, as well. A smaller subset of the independent
feature list can be applied to those devices.
Transfer (Register 0xFF)
All registers except Register 0x100 are updated the moment
they are written. Setting Bit 0 of this transfer register high
initializes the settings in the ADC sample rate override register
(Address 0x100).
Power Modes (Register 0x08)
Bits[7:6]—Open
Bit 5—External Power-Down Pin Function
If set, the external PDWN pin initiates standby mode. If cleared,
the external PDWN pin initiates power-down mode.
Bits[4:2]—Open
Bits[1:0]—Internal Power-Down Mode
In normal operation (Bits[1:0] = 00), all ADC channels are
active.
In power-down mode (Bits[1:0] = 01), the digital data path clocks
are disabled while the digital data path is reset. Outputs are
disabled.
In standby mode (Bits[1:0] = 10), the digital data path clocks
and the outputs are disabled.
During a digital reset (Bits[1:0] = 11), all the digital data path
clocks and the outputs (where applicable) on the chip are reset,
except the SPI port. Note that the SPI is always left under
control of the user, that is, it is never automatically disabled or
in reset (except by power-on reset).
Enhancement Control (Register 0x0C)
Bits[7:3]—Open
Bit 2—Chop Mode
For applications that are sensitive to offset voltages and other
low frequency noise, such as homodyne or direct conversion
receivers, chopping in the first stage of the
that can be enabled by setting Bit 2. In the frequency domain,
chopping translates offsets and other low frequency noise to
f
Bits[1:0]—Open
CLK
/2, where they can be filtered.
AN-877
AD9257
Application Note,
is a feature
Rev. 0 | Page 34 of 40
Output Mode (Register 0x14)
Bit 7—Open
Bit 6—LVDS-ANSI/LVDS-IEEE Option
Setting this bit chooses the LVDS-IEEE (reduced range) option.
The default setting is LVDS-ANSI. As described in Table 18,
when LVDS-ANSI or LVDS-IEEE reduced range link is selected,
the user can select the driver termination. The driver current
is automatically selected to give the proper output swing.
Table 18. LVDS-ANSI/LVDS-IEEE Options
Output
Mode,
Bit[6]
0
1
Bits[5:3]—Open
Bit 2—Output Invert
Setting this bit inverts the output bit stream.
Bit 1—Open
Bit 0—Output Format
By default, this bit is set to send the data output in twos
complement format. Resetting this bit changes the output mode
to offset binary.
Output Adjust (Register 0x15)
Bits[7:6]—Open
Bits[5:4]—Output Termination
These bits allow the user to select the internal termination
resistor.
Bits[3:1]—Open
Bit 0—Output Drive
Bit 0 of the output adjust register controls the drive strength on
the LVDS driver of the FCO and DCO outputs only. The default
values set the drive to 1×. The drive can be increased to 2× by
setting the appropriate channel bit in Register 0x05 and then
setting Bit 0. These features cannot be used with the output driver
termination select. The termination selection takes precedence
over the 2× driver strength on FCO and DCO when both the
output driver termination and output drive are selected.
Output Mode
LVDS-ANSI
LVDS-IEEE
reduced range
link
Output
Driver
Termination
User
selectable
User
selectable
Data Sheet
Output Driver
Current
Automatically
selected to give
proper swing
Automatically
selected to give
proper swing