AD9257 Analog Devices, AD9257 Datasheet - Page 35

• Manufacturer Part Number: AD9257
• Description: Octal, 14-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter
• Manufacturer: Analog Devices

Data Sheet
Output Phase (Register 0x16)
Bit 7—Open
Bits[6:4]—Input Clock Phase Adjust
Table 19. Input Clock Phase Adjust Options
Input Clock Phase
Adjust, Bits[6:4]
000 (Default)
001
010
011
100
101
110
111
Bits[3:0]—Output Clock Phase Adjust
Table 20. Output Clock Phase Adjust Options
Output Clock (DCO),
Phase Adjust, Bits[3:0]
0000
0001
0010
0011 (Default)
0100
0101
0110
0111
1000
1001
1010
1011
Number of Input Clock Cycles of
Phase Delay
0
1
2
3
4
5
6
7
DCO Phase Adjustment
(Degrees Relative to D± x Edge)
0
60
120
180
240
300
360
420
480
540
600
660
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Resolution/Sample Rate Override (Register 0x100)
This register is designed to allow the user to downgrade the device.
Any attempt to upgrade the default speed grade results in a chip
power-down. Settings in this register are not initialized until Bit 0
of the transfer register (Register 0xFF) is written high.
User I/O Control 2 (Register 0x101)
Bits[7:1]—Open
Bit 0—SDIO Pull-Down
Bit 0 can be set to disable the internal 30 kΩ pull-down on the
SDIO pin, which can be used to limit loading when many
devices are connected to the SPI bus.
User I/O Control 3 (Register 0x102)
Bits[7:4]—Open
Bit 3—VCM Power-Down
Bit 3 can be set high to power down the internal VCM
generator. This feature is used when applying an external
reference.
Bits[2:0]—Open
AD9257