AD9613

Manufacturer Part NumberAD9613
Description12-bit, 170/210/250 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
ManufacturerAnalog Devices
AD9613 datasheet
 

Specifications of AD9613

Resolution (bits)12bit# Chan2
Sample Rate250MSPSInterfaceLVDS,Par
Analog Input TypeDiff-BipAin Range1.75 V p-p
Adc ArchitecturePipelinedPkg TypeCSP
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Data Sheet
FEATURES
SNR = 69.6 dBFS at 185 MHz f
and 250 MSPS
IN
SFDR = 86 dBc at 185 MHz f
and 250 MSPS
IN
−149.9 dBFS/Hz input noise at 185 MHz, −1 dBFS A
250 MSPS
Total power consumption: 770 mW at 250 MSPS
1.8 V supply voltages
LVDS (ANSI-644 levels) outputs
Integer 1-to-8 input clock divider (625 MHz maximum input)
Sample rates of up to 250 MSPS
IF sampling frequencies of up to 400 MHz
Internal ADC voltage reference
Flexible analog input range
1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
ADC clock duty cycle stabilizer
95 dB channel isolation/crosstalk
Serial port control
Energy-saving power-down modes
User-configurable, built-in self test (BIST) capability
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers (3G)
TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
I/Q demodulation systems
Smart antenna systems
General-purpose software radios
Ultrasound equipment
Broadband data applications
GENERAL DESCRIPTION
The
AD9613
is a dual 12-bit, analog-to-digital converter (ADC)
with sampling speeds of up to 250 MSPS. The AD9613 is designed
to support communications applications where low cost, small
size, wide bandwidth, and versatility are desired.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of user-
selectable input ranges. An integrated voltage reference eases design
considerations. A duty cycle stabilizer (DCS) is provided to
compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
The ADC output data is routed directly to the two external 12-bit
LVDS output ports and formatted as either interleaved or channel
multiplexed.
Flexible power-down options allow significant power savings,
when desired.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
12-Bit, 170 MSPS/210 MSPS/250 MSPS,
1.8 V Dual Analog-to-Digital Converter (ADC)
FUNCTIONAL BLOCK DIAGRAM
and
VIN+A
IN
VIN–A
AD9613
VCM
VIN+B
VIN–B
REFERENCE
SCLK
NOTES
1. THE D0± TO D11± PINS REPRESENT BOTH THE CHANNEL A
AND CHANNE L B LVDS OUTPUT DATA.
Programming for setup and control is accomplished using a
3-wire SPI-compatible serial interface.
The AD9613 is available in a 64-lead LFCSP and is specified
over the industrial temperature range of −40°C to +85°C. This
product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
1. Integrated dual, 12-bit, 170 MSPS/210 MSPS/250 MSPS ADCs.
2. Fast overrange and threshold detect.
3. Proprietary differential input maintains excellent SNR
performance for input frequencies of up to 400 MHz.
4. SYNC input allows synchronization of multiple devices.
5. 3-pin, 1.8 V SPI port for register programming and register
readback.
6. Pin compatibility with the AD9643, allowing a simple
migration up to 14 bits, and with the
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
AD9613
AVDD
AGND
DRVDD
PIPELINE
12
12-BIT
ADC
PARALLEL
DDR LVDS
AND
PIPELINE
12
DRIVERS
12-BIT
ADC
1 TO 8
SERIAL PORT
CLOCK
DIVIDER
SDIO
CSB
CLK+
CLK–
SYNC
Figure 1.
AD6649
and the AD6643.
www.analog.com
©2011 Analog Devices, Inc. All rights reserved.
D0±
.
.
.
.
.
D11±
DCO±
OR±
OEB
PDWN

AD9613 Summary of contents

  • Page 1

    ... GENERAL DESCRIPTION The AD9613 is a dual 12-bit, analog-to-digital converter (ADC) with sampling speeds 250 MSPS. The AD9613 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic ...

  • Page 2

    ... Changes to Bit 0—Master Sync Buffer Enable Section ............. 34 Deleted SYNC Pin Control (Register 0x59) Section.................. 34 5/11—Rev Rev. A Changes to Table 2, AD9613-170: Worst Second or Third Harmonic and Worst Other (Harmonic or Spur) Max Values and Spurious Free Dynamic Range Min Value .............................4 4/11—Revision 0: Initial Version Rev ...

  • Page 3

    ... AD9613 Unit Bits mV %FSR LSB LSB LSB LSB mV %FSR ppm/°C ppm/°C LSB rms V p-p pF kΩ ...

  • Page 4

    ... Full 25°C −80 25°C 94 25°C 92 Full 78 80 25°C 87 25°C 89 Full 25°C 83 25°C −97 25°C −96 Full −78 25°C −97 25°C −91 Full 25°C −93 Rev Page Data Sheet AD9613-250 Typ Max Min Typ Max 70.1 70.0 70.0 69.8 69.8 69.6 69.5 69.2 67.8 69.3 69.0 69.1 69.0 69.0 68.8 68.8 68.6 68.5 68.2 66.5 68.3 68.0 11.2 11.2 11.2 11.1 11.1 11.1 11.1 11 ...

  • Page 5

    ... Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally. AD9613-170 AD9613-210 Temp Min Typ Max Min 25°C 88 Full 95 25°C 400 25°C 1000 Rev Page AD9613 AD9613-250 Typ Max Min Typ Max 400 400 1000 1000 Unit dBc dB MHz ...

  • Page 6

    ... AD9613 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.75 V p-p full-scale input range, DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range ...

  • Page 7

    ... Reduced Swing Mode OS 1 Pull up. 2 Pull down. Temp Min Full 1.22 Full 0 Full 45 Full −5 Full Full Full 250 Full 1.15 Full 150 Full 1.15 Rev Page AD9613 Typ Max Unit 2 μA +5 μA 26 kΩ 350 450 mV 1.22 1.35 V 200 280 mV 1.22 1.35 ...

  • Page 8

    ... Full 40 170 40 Full 5.8 4.8 Full 2.61 2.9 3.19 2.16 Full 2.76 2.9 3.05 2.28 Full 0.8 0.8 Full 1.0 Full 0.1 Full 4.8 Full 5.5 Full 0.3 0.7 1.1 0.3 Full 10 Full 1.0 Full 0.1 Full 10 Full 250 Full 3 Rev Page Data Sheet AD9613-250 Typ Max Min Typ Max Unit 625 625 MHz 210 40 250 MSPS 4 ns 2.4 2.64 1.8 2.0 2.2 ns 2.4 2.52 1.9 2.0 2.1 ns 0.8 ns 1.0 1.0 ns 0.1 0.1 ps rms 4.8 4.8 ns 5.5 5.5 ns 0.7 1.1 0.3 0.7 1.1 ...

  • Page 9

    ... Time required for the SDIO pin to switch from an input to an output EN_SDIO relative to the SCLK falling edge (not shown in Figure 58) t Time required for the SDIO pin to switch from an output to an input DIS_SDIO relative to the SCLK rising edge (not shown in Figure 58) Rev Page AD9613 Min Typ Max Unit 0.3 ns 0.4 ...

  • Page 10

    ... AD9613 Timing Diagrams VIN CLK+ CLK– DCO– DCO+ PARALLEL INTERLEAVED D0± (LSB CHANNEL A AND . CHANNEL B D11± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL A . D10±/D11± (MSB) CHANNEL MULTIPLEXED D0±/D1± (EVEN/ODD) MODE (LSB CHANNEL B . D10± ...

  • Page 11

    ... ESD CAUTION Rev Page specified for a 4-layer PCB with solid ground addition, metal in direct contact with the Airflow Velocity (m/sec) θ θ 26.8 1.14 1.0 21.6 2.0 20.2 AD9613 1, 4 θ Unit JB 10.4 °C/W °C/W °C/W ...

  • Page 12

    ... VCM 61 VIN−B 62 VIN+B Digital Input 3 SYNC PIN 1 CLK+ 1 CLK– 2 SYNC 3 DNC 4 DNC 5 DNC 6 AD9613 DNC 7 PARALLEL LVDS DNC 8 TOP VIEW DNC 9 (Not to Scale) DRVDD 10 DNC 11 DNC D1– 15 D1+ 16 PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PADDLE MUST BE CONNECTED TO GROUND FOR PROPER OPERATION ...

  • Page 13

    ... SPI Serial Data I/O. Input SPI Chip Select (Active Low). Input/Output Output Enable Bar Input (Active Low). Input/Output Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14. Rev Page AD9613 ...

  • Page 14

    ... VCM 1 CLK+ 2 CLK− Digital Input 3 SYNC Digital Outputs 7 ORB+ 6 ORB− PIN 1 CLK+ 1 CLK– 2 SYNC 3 DNC 4 DNC 5 AD9613 ORB– 6 CHANNEL ORB+ 7 MULTIPLEXED DNC 8 (EVEN/ODD) DNC 9 LVDS 10 TOP VIEW 11 (Not to Scale Type Description Supply Digital Output Driver Supply (1.8 V Nominal). ...

  • Page 15

    ... SPI Serial Data I/O. Input SPI Chip Select (Active Low). Input Output Enable Bar Input (Active Low). Input Power-Down Input (Active High). Operation depends upon SPI mode; this input can be configured as power-down or standby. For further description, refer to Table 14. Rev Page AD9613 ...

  • Page 16

    ... MHz Figure 10. AD9613-170 Single-Tone SNR/SFDR vs. Input Frequency (f IN 170MSPS 305.1MHz @ –1dBFS SNR = 67dB (68dBFS) SFDR = 79dBc SECOND HARMONIC 305.1 MHz Figure 11. AD9613-170 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN Rev Page 120 SFDR (dBFS) 100 80 SNR (dBFS) 60 SFDR (dBc) 40 SNR (dBc) ...

  • Page 17

    ... FREQUENCY (MHz) Figure 14. AD9613-170 Two-Tone FFT with f IN1 f = 170 MSPS S –32.5 –21.0 –7.0 Figure 15. AD9613-170 Single-Tone SNR/SFDR vs. Sample Rate (f = 170 MSPS 89.12 92.12 MHz, IN2 184.12 187.12 MHz, IN2 Rev Page 100 95 90 ...

  • Page 18

    ... MHz Figure 21. AD9613-210 Single-Tone SNR/SFDR vs. Input Frequency (f IN –100 –120 100 = 305.1 MHz Figure 22. AD9613-210 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN SNR (dBc) –100 –120 –30 –20 – with IN Input Amplitude (A Rev Page SFDR (dBc) ...

  • Page 19

    ... Figure 25. AD9613-210 Two-Tone FFT with f IN1 f = 210 MSPS S 100 100 120 140 SAMPLE RATE (MSPS) Figure 26. AD9613-210 Single-Tone SNR/SFDR vs. Sample Rate (f with MHz 100 = 89.12 92.12 MHz, IN2 100 = 184.12 187.12 MHz, IN2 SNR, CHANNEL B SFDR, CHANNEL B ...

  • Page 20

    ... FREQUENCY (MHz) Figure 32. AD9613-250 Single-Tone SNR/SFDR vs. Input Frequency (f SECOND HARMONIC 80 90 100 110 120 = 305.1 MHz Figure 33. AD9613-250 Two-Tone SFDR/IMD3 vs. Input Amplitude (A IN SNR (dBc) –30 –20 – with IN Input Amplitude (A 200 220 240 260 Figure 35 ...

  • Page 21

    ... SAMPLE RATE (MSPS) Figure 37. AD9613-250 Single-Tone SNR/SFDR vs. Sample Rate (f with f = 90.1 MHz 100 110 120 = 184.12 187.12 MHz, IN2 SNR, CHANNEL B SFDR, CHANNEL B SNR, CHANNEL A SFDR, CHANNEL A 180 200 220 240 ...

  • Page 22

    ... AD9613 EQUIVALENT CIRCUITS AVDD VIN Figure 39. Equivalent Analog Input Circuit AVDD AVDD 0.9V 15kΩ 15kΩ CLK+ Figure 40. Equivalent Clock lnput Circuit DRVDD V+ V– DATAOUT– DATAOUT+ V– V+ Figure 41. Equivalent LVDS Output Circuit DRVDD 350Ω SDIO 26kΩ Figure 42. Equivalent SDIO Circuit ...

  • Page 23

    ... VIN+ and VIN− should be matched, and the inputs should be differentially balanced. Input Common Mode The analog inputs of the AD9613 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that V 0 recommended for optimum performance. An on-board common-mode voltage reference is included in the design and is available from the VCM pin ...

  • Page 24

    ... ADC. The output common-mode voltage of the ADA4930-2 is easily set with the VCM pin of the AD9613 (see Figure 47), and the driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal. 200Ω ...

  • Page 25

    ... Jitter Considerations section. Figure 52 and Figure 53 show two preferable methods for clocking the AD9613 (at clock rates 625 MHz). A low jitter clock source is converted from a single-ended signal to a differential signal using an RF balun or RF transformer. ...

  • Page 26

    ... The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9613. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators make the best clock sources ...

  • Page 27

    ... Timing The AD9613 provides latched data with a pipeline delay of 10 input sample clock cycles. Data outputs are available one propagation delay (t PD Minimize the length of the output data lines and loads placed on them to reduce transients within the AD9613 ...

  • Page 28

    ... AD9613 CHANNEL/CHIP SYNCHRONIZATION The AD9613 has a SYNC input that allows the user flexible synchronization options for synchronizing the internal blocks. The sync feature is useful for guaranteeing synchronized operation across multiple ADCs. The input clock divider can be synchronized using the SYNC input. The divider can be enabled to synchronize on a single occurrence of the SYNC signal or on every occurrence by setting the appropriate bits in Register 0x3A ...

  • Page 29

    ... Data Sheet SERIAL PORT INTERFACE (SPI) The AD9613 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. The SPI gives the user added flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port ...

  • Page 30

    ... SPI. These features are described in detail in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. The AD9613 part-specific features are described in the Memory Map Register Description section. Table 13. Features Accessible Using the SPI Feature Name Mode ...

  • Page 31

    ... Address 0x13), this address location should not be written. Default Values After the AD9613 is reset, critical registers are loaded with default values. The default values for the registers are given in the memory map register table (see Table 14). Logic Levels An explanation of logic level terminology follows: • ...

  • Page 32

    ... Open (global) 0x0B Clock divide Open Open (global) Bit 5 Bit 4 Bit 3 Bit 2 Soft reset 1 1 Soft reset 8-bit chip ID[7:0] (AD9613 = 0x83) (default) Open Open Speed grade 250 MSPS 01 = 210 MSPS 11 = 170 MSPS Open Open Open Open Open Open Open Open ...

  • Page 33

    ... Open Open 0x00 0x00 … 0x00 … … 0x00 0x00 0x00 0x00 0x00 AD9613 Default Notes/ Comments When this register is set, the test data is placed on the output pins in place of normal data Configures the outputs and the format of ...

  • Page 34

    ... AD9613 Addr Register Bit 7 Bit 6 (Hex) Name (MSB) Pattern 3 LSB (global) 0x1E User Test Pattern 3 MSB (global) 0x1F User Test Pattern 4 LSB (global) 0x20 User Test Pattern 4 MSB (global) 0x24 BIST signature LSB (local) 0x25 BIST signature MSB (local) 0x3A Sync control ...

  • Page 35

    ... Figure 48. For optimal channel-to-channel isolation Ω resistor should be included between the AD9613 VCM pin and the Channel A analog input network connection, as well as between the AD9613 VCM pin and the Channel B analog input network connection. SPI Port The SPI port should not be active during periods when the full dynamic performance of the converter is required ...

  • Page 36

    ... Lead Frame Chip Scale Package [LFCSP_VQ], 170 MSPS 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 210 MSPS 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 250 MSPS Evaluation Board with AD9613, 170 MSPS Evaluation Board with AD9613, 210 MSPS Evaluation Board with AD9613, 250 MSPS D09637-0-9/11(B) Rev ...