AD9650 Analog Devices, AD9650 Datasheet - Page 32

• Manufacturer Part Number: AD9650
• Description: 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS Analog-to-Digital Converter
• Manufacturer: Analog Devices

Specifications of AD9650

• Resolution (bits): 16bit
• # Chan: 2
• Sample Rate: 105MSPS
• Interface: LVDS,Par
• Analog Input Type: Diff-Bip
• Ain Range: (2Vref) p-p,2.7 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9650
VOLTAGE REFERENCE
The
reference or a user-applied external reference. The input range
of the ADC always equals twice the voltage at the reference pin
(VREF) for either an internal or an external reference. Table 11
shows a summary of the internal and external reference
connections.
Internal Reference Connection
A stable and accurate 1.35 V reference is built into the AD9650,
allowing a 2.7 V p-p full-scale input. To configure the
for an internal reference, the SENSE pin must be tied low. In
addition, to achieve optimal noise performance, it is recommended
that the VREF pin be decoupled by 1.0 µF and 0.1 µF capacitors
close to the pin. Figure 83 shows the configuration for the internal
reference connection.
If the internal reference of the
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 84 shows
how the internal reference voltage is affected by loading.
Table 11. Reference Configuration Summary
Selected Mode
Internal Reference
External Reference
AD9650
1.0µF
can be configured for a stable 1.35 V internal
Figure 83. Internal Reference Configuration
0.1µF
VIN+A/VIN+B
VIN–A/VIN–B
SENSE
VREF
AD9650
SENSE Voltage (V)
AGND to 0.2
AVDD
SELECT
LOGIC
is used to drive multiple
V
SELECT
AD9650
CORE
ADC
AD9650
Resulting VREF (V)
1.35
N/A
Rev. A | Page 32 of 44
External Reference Operation
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift charac-
teristics. Figure 85 shows the typical drift characteristics of the
internal reference in 1.35 V mode.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
reference buffer loads the external reference with an equivalent
6 kΩ load (see Figure 75). The internal buffer generates the
positive and negative full-scale references for the ADC core.
Therefore, the external reference must be limited to a maximum
of 1.35 V.
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–1
–2
–3
–4
–5
–6
0
0
–50
0
Figure 84. Reference Voltage Error vs. Load Current
–30
0.2
Figure 85. Typical VREF Drift
Resulting Differential Span (V p-p)
2.7
2 × external reference
–10
0.4
LOAD CURRENT (mA)
TEMPERATURE (°C)
0.6
10
0.8
30
1.0
50
Data Sheet
1.2
70
1.4
90