AD9122 Analog Devices, AD9122 Datasheet - Page 20

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
SERIAL PORT OPTIONS
The serial port can support both MSB first and LSB first data
formats. This functionality is controlled by the LSB_FIRST bit
(Register 0x00, Bit 6). The default is MSB first (LSB_FIRST = 0).
When LSB_FIRST = 0 (MSB first), the instruction and data bits
must be written from MSB to LSB. Multibyte data transfers in
MSB first format start with an instruction byte that includes the
register address of the most significant data byte. Subsequent
data bytes should follow from high address to low address. In
MSB first mode, the serial port internal byte address generator
decrements for each data byte of the multibyte communication
cycle.
When LSB_FIRST = 1 (LSB first), the instruction and data bits
must be written from LSB to MSB. Multibyte data transfers in
LSB first format start with an instruction byte that includes the
register address of the least significant data byte. Subsequent
data bytes should follow from low address to high address. In
LSB first mode, the serial port internal byte address generator
increments for each data byte of the multibyte communication
cycle.
If the MSB first mode is active, the serial port controller data
address decrements from the data address written toward 0x00
for multibyte I/O operations. If the LSB first mode is active, the
serial port controller data address increments from the data
address written toward 0x7F for multibyte I/O operations.
SCLK
SDIO
SDO
CS
R/W A6 A5
Figure 39. Serial Port Interface Timing, MSB First
INSTRUCTION CYCLE
A4 A3
A2 A1
A0 D7
D7
N
N
DATA TRANSFER CYCLE
D6
D6
N
N
D5
D5
N
N
D3
D3
0
0
D2
D2
0
0
D1
D1
0
0
D0
D0
0
0
Rev. B | Page 20 of 60
SCLK
SCLK
SCLK
SDIO,
SDIO
SDIO
SDO
SDO
CS
CS
CS
Figure 41. Timing Diagram for Serial Port Register Write
Figure 42. Timing Diagram for Serial Port Register Read
A0
Figure 40. Serial Port Interface Timing, LSB First
t
INSTRUCTION CYCLE
DCSB
A1 A2
INSTRUCTION BIT 7
t
DS
DATA BIT n
A3 A4
t
PWH
t
t
DH
DV
t
A5 A6
SCLK
t
PWL
R/W
INSTRUCTION BIT 6
DATA BIT n – 1
D0
D0
0
0
DATA TRANSFER CYCLE
D1
D1
0
0
D2
D2
0
0
D4
D4
N
N
D5
D5
N
N
D6
D6
N
N
D7
D7
N
N