AD9122 Analog Devices, AD9122 Datasheet - Page 26

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
Register
Name
Sync Status
Data
Receiver
Status
DCI Delay
FIFO
Control
FIFO Status
Address
(Hex)
0x12
0x13
0x15
0x16
0x17
0x18
0x19
Bits
7
6
[7:0]
5
4
3
2
1
0
[1:0]
[2:0]
7
6
2
1
[7:0]
Name
Sync lost
Sync locked
Sync Phase Readback[7:0]
LVDS FRAME level high
LVDS FRAME level low
LVDS DCI level high
LVDS DCI level low
LVDS data level high
LVDS data level low
DCI Delay[1:0]
FIFO Phase Offset[2:0]
FIFO Warning 1
FIFO Warning 2
FIFO soft align
acknowledge
FIFO soft align request
FIFO Level[7:0]
Rev. B | Page 26 of 60
1 = synchronization was attained but has been lost.
1 = synchronization has been attained.
Indicates the averaged sync phase offset (6.2 format). If
this value differs from the Sync Phase Request[5:0] value
in Register 0x11, a sync timing error has occurred. For more
information, see the Sync Status Bits section.
00000000 = 0.0.
00000001 = 0.25.
…
11111110 = 63.50.
11111111 = 63.75.
One or both LVDS FRAME input signals have exceeded 1.7 V.
One or both LVDS FRAME input signals have crossed below
0.7 V.
One or both LVDS DCI input signals have exceeded 1.7 V.
One or both LVDS DCI input signals have crossed
below 0.7 V.
One or more LVDS Dx input signals have exceeded 1.7 V.
One or more LVDS Dx input signals have crossed below 0.7 V.
This option is available for the Revision 2 silicon only. The
DCI delay bits control the delay applied to the DCI signal.
The DCI delay affects the sampling interval of the DCI with
respect to the Dx inputs. See Table 13.
00 = 350 ps delay of DCI signal.
01 = 590 ps delay of DCI signal.
10 = 800 ps delay of DCI signal.
11 = 925 ps delay of DCI signal.
FIFO write pointer phase offset following FIFO reset. This
is the difference between the read pointer and the write
pointer values upon FIFO reset. The optimal value is
nominally 4 (100).
000 = 0.
001 = 1.
…
111 = 7.
1 = FIFO read and write pointers are within ±1.
1 = FIFO read and write pointers are within ±2.
1 = FIFO read and write pointers are aligned after a serial
port initiated FIFO reset.
1 = request FIFO read and write pointer alignment via the
serial port.
Thermometer encoded measure of the FIFO level.
Description
Default
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
00
100
N/A
N/A
N/A
0
N/A