AD9122 Analog Devices, AD9122 Datasheet - Page 24

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

AD9122
Register
Name
Interrupt
Enable
Event Flag
Clock
Receiver
Control
PLL Control
Address
(Hex)
0x05
0x06
0x07
0x08
0x0A
0x0C
Bits
[7:5]
4
3
2
[1:0]
7
6
5
4
1
0
4
3
2
7
6
5
4
7
6
[5:0]
[7:6]
[4:0]
Name
Set to 0
Enable AED compare pass
Enable AED compare fail
Enable SED compare fail
Set to 0
PLL lock lost
PLL locked
Sync signal lost
Sync signal locked
FIFO Warning 1
FIFO Warning 2
Note that all event flags are cleared by writing the respective bit high.
AED compare pass
AED compare fail
SED compare fail
Note that all event flags are cleared by writing the respective bit high.
DACCLK duty correction
REFCLK duty correction
DACCLK cross-correction
REFCLK cross-correction
PLL enable
PLL manual enable
Manual VCO Band[5:0]
PLL Loop Bandwidth[1:0]
PLL Charge Pump
Current[4:0]
Rev. B | Page 24 of 60
1 = indicates that the SED logic detected a valid input data
pattern compared against the preprogrammed expected
values. This is a latched signal.
1 = indicates that the SED logic detected an invalid input
data pattern compared against the preprogrammed
expected values. This latched signal is automatically cleared
when eight valid I/Q data pairs are received.
1 = indicates that the SED logic detected an invalid input
data pattern compared against the preprogrammed
expected values. This is a latched signal.
1 = enable duty cycle correction on the DACCLK input.
1 = enable duty cycle correction on the REFCLK input.
1 = enable differential crossing correction on the DACCLK
input.
1 = enable differential crossing correction on the REFCLK
input.
1 = enable the PLL clock multiplier. The REFCLK input is used
as the PLL reference clock signal.
1 = enable manual selection of the VCO band. The correct
VCO band must be determined by the user and written to
Bits[5:0].
Selects the VCO band to be used.
Selects the PLL loop filter bandwidth.
00 = widest bandwidth.
…
11 = narrowest bandwidth.
Sets the nominal PLL charge pump current.
00000 = lowest current setting.
…
11111 = highest current setting.
Description
Set these bits to 0.
1 = enable interrupt for AED comparison pass.
1 = enable interrupt for AED comparison fail.
1 = enable interrupt for SED comparison fail.
Set these bits to 0.
1 = indicates that the PLL, which had been previously
locked, has unlocked from the reference signal. This is a
latched signal.
1 = indicates that the PLL has locked to the reference
clock input.
1 = indicates that the sync logic, which had been previously
locked, has lost alignment. This is a latched signal.
1 = indicates that the sync logic has achieved sync
alignment. This is indicated when no phase changes
were requested for at least a few full averaging cycles.
1 = indicates that the difference between the FIFO read
and write pointers is 1.
1 = indicates that the difference between the FIFO read
and write pointers is 2.
Default
000
0
0
0
00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0
0
1
1
0
1
000000
11
10001