AD9122 Analog Devices, AD9122 Datasheet - Page 3

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

REVISION HISTORY
5/11—Rev. A to Rev. B
Change to General Description Section ......................................... 1
Added Companion Products Section ............................................. 1
Moved Power Supply Rejection Ratio Parameter from Power
Consumption Section of Table 1 to Main DAC Outputs Section
of Table 1 ............................................................................................. 5
Moved Power-Up Time Parameter from Table 3 to Table 1 ........ 5
Changed Maximum Clock Rate Parameter in Table 2 ................. 6
Changes to Table 3 ............................................................................ 6
Changes to Table 5 ............................................................................ 7
Changes to Table 6 ............................................................................ 8
Changes to Figure 3 and Table 8 ..................................................... 9
Changes to Differences Between AD9122R1 and AD9122R2
Section and Device Marking of AD9122R1 and AD9122R2
Section .............................................................................................. 18
Changes to Figure 40 and Figure 41 ............................................. 20
Changes to Table 10 ........................................................................ 21
Changes to Table 11 ........................................................................ 23
Changes to LVDS Input Data Ports Section and Figure 45 ....... 32
Moved Interface Timing Section ................................................... 32
Moved Figure 46 and Table 13; Changes to Interface
Timing Section ................................................................................ 33
Changes to Resetting the FIFO Section, Serial Port Initiated
FIFO Reset Section, and Figure 48 ............................................... 34
Changes to FRAME Initiated Absolute FIFO Reset Section
and Monitoring the FIFO Status Section ..................................... 35
Changes to Table 22 ........................................................................ 42
Changes to Inverse Sinc Filter Section ......................................... 43
Change to Driving the DACCLK and REFCLK Inputs Section .... 44
Changes to Manual VCO Band Select Section ............................ 45
Changes to Transmit DAC Operation Section ............................ 46
Changes to Figure 69, Figure 70, Figure 71, and Figure 72 ....... 47
Changes to Power Dissipation Section ......................................... 50
Replaced Temperature Sensor Section ......................................... 51
Changes to Multichip Synchronization Section, Synchronization
with Clock Multiplication Section, and Procedure for
Synchronization When Using the PLL Section ........................... 52
Changes to Procedure for Data Rate Synchronization When
Directly Sourcing the DAC Sampling Clock Section ................. 53
Rev. B | Page 3 of 60
Moved Table 25 and Figure 85 ...................................................... 54
Changes to Procedure for FIFO Rate Synchronization When
Directly Sourcing the DAC Sampling Clock Section ................. 54
Changes to Additional Synchronization Features Section and
Timing Optimization Section ........................................................ 55
Added One-Time Synchronization Section ................................ 55
Changes to Interrupt Request Operation Section ...................... 56
Changes to SED Operation Section .............................................. 57
Changes to SED Example Section ................................................. 58
Changes to Example Start-Up Routine Section .......................... 59
3/10—Rev. 0 to Rev. A
Changes to Reflect Differences Between R1 and R2
Silicon .................................................................................. Universal
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Table 5 ............................................................................ 7
Change to IOVDD Rating in Table 6 ............................................. 8
Changes to Table 8 ............................................................................ 9
Changes to Figure 10 through Figure 15 ...................................... 12
Added Differences Between AD9122R1 and AD9122R2
Section; Added Figure 36 and Figure 37; Renumbered Figures
Sequentially ...................................................................................... 18
Changes to Table 10 ........................................................................ 21
Changes to Table 11 ........................................................................ 23
Changes to FIFO Operation Section ............................................ 33
Changes to Resetting the FIFO Section; Replaced Table 13;
Added Serial Port Initiated FIFO Reset Section and FRAME
Initiated Relative FIFO Reset Section ........................................... 34
Added FRAME Initiated Absolute FIFO Reset Section;
Replaced Table 14 ............................................................................ 35
Changes to Figure 54 ...................................................................... 38
Changes to Table 18 ........................................................................ 39
Changes to SED Example Section ................................................. 58
Added Example Start-Up Routine Section .................................. 59
9/09—Revision 0: Initial Version
AD9122