AD9122 Analog Devices, AD9122 Datasheet - Page 25

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Register
Name
PLL Control
PLL Status
Sync
Control
Address
(Hex)
0x0D
0x0E
0x0F
0x10
0x11
Bits
[7:6]
4
[3:2]
[1:0]
7
[3:0]
[5:0]
7
6
3
[2:0]
[5:0]
Name
N2[1:0]
PLL cross-control enable
N0[1:0]
N1[1:0]
PLL locked
VCO Control Voltage[3:0]
VCO Band Readback[5:0]
Sync enable
Data/FIFO rate toggle
Rising edge sync
Sync Averaging[2:0]
Sync Phase Request[5:0]
Rev. B | Page 25 of 60
Description
PLL control clock divider. This divider determines the ratio of
the DACCLK frequency to the PLL controller clock frequency.
f
00 = f
01 = f
10 = f
11 = f
1 = enable PLL cross-point controller.
PLL VCO divider. This divider determines the ratio of the VCO
frequency to the DACCLK frequency.
00 = f
01 = f
10 = f
11 = f
PLL loop divider. This divider determines the ratio of the
DACCLK frequency to the REFCLK frequency.
00 = f
01 = f
10 = f
11 = f
1 = the PLL-generated clock is tracking the REFCLK input
signal.
VCO control voltage readback. See Table 24.
Indicates the VCO band currently selected.
1 = enable the synchronization logic.
0 = operate the synchronization at the FIFO reset rate.
1 = operate the synchronization at the data rate.
0 = sync is initiated on the falling edge of the sync input.
1 = sync is initiated on the rising edge of the sync input.
Sets the number of input samples that are averaged in
determining the sync phase.
000 = 1.
001 = 2.
010 = 4.
011 = 8.
100 = 16.
101 = 32.
110 = 64.
111 = 128.
This register sets the requested clock phase offset after sync.
The offset unit is in DACCLK cycles. This register enables
repositioning of the DAC output with respect to the sync
input. The offset can also be used to skew the DAC outputs
between the synchronized DACs.
000000 = 0 DACCLK cycles.
000001 = 1 DACCLK cycle.
…
111111 = 63 DACCLK cycles.
PC_CLK
DACCLK
DACCLK
DACCLK
DACCLK
VCO
VCO
VCO
VCO
DACCLK
DACCLK
DACCLK
DACCLK
must always be less than 75 MHz.
/f
/f
/f
/f
DACCLK
DACCLK
DACCLK
DACCLK
/f
/f
/f
/f
/f
/f
/f
/f
PC_CLK
PC_CLK
PC_CLK
PC_CLK
REFCLK
REFCLK
REFCLK
REFCLK
= 1.
= 2.
= 4.
= 4.
= 2.
= 4.
= 8.
= 16.
= 2.
= 4.
= 8.
= 16.
Default
11
1
10
01
N/A
N/A
N/A
0
1
1
000
000000
AD9122