AD9122 Analog Devices, AD9122 Datasheet - Page 53

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

To maintain synchronization, the skew between the REFCLK
signals of the devices must be less than t
the FIFO, the FRAME signal must be held high for the time
interval required to write two complete input data words. A
timing diagram of the input signals is shown in Figure 82.
Figure 82 shows a REFCLK frequency equal to the data rate.
Although this is the most common situation, it is not strictly
required for proper synchronization. Any REFCLK frequency
that satisfies the following equation is acceptable. (This
equation is valid only when the PLL is used because only data
rate mode is available with the PLL on.)
where N = 0, 1, 2, or 3.
As an example, a configuration with 4× interpolation and clock
frequencies of f
200 MHz, and f
SYNCHRONIZATION WITH DIRECT CLOCKING
When directly sourcing the DAC sample rate clock, a separate
REFCLK input signal is required for synchronization. To syn-
chronize devices, the DACCLK signal and the REFCLK signal
must be distributed with low skew to all the devices being
synchronized. If the devices need to be synchronized to a
f
SYNC_I
= f
DACCLK
VCO
SYNC_I
/2
= 1600 MHz, f
N
= 100 MHz is a viable solution.
and f
SYNC_I
REFCLKP(1)/
REFCLKP(2)/
REFCLKN(1)
REFCLKN(2)
RATE CLOCK
FRAMEP(2)/
FRAMEN(2)
≤ f
DACCLK
SAMPLE
CLOCK
SYNC
DCIP(2)/
DCIN(2)
DATA
FPGA
Figure 83. Typical Circuit Diagram for Synchronizing Devices to a System Clock
= 800 MHz, f
SKEW
CLOCK DRIVER
CLOCK DRIVER
Figure 82. Timing Diagram Required for Synchronizing Devices
LOW SKEW
LOW SKEW
ns. When resetting
t
SKEW
DATA
LENGTH TRACES
t
SDCI
=
MATCHED
Rev. B | Page 53 of 60
t
HDCI
master clock, use the master clock directly for generating the
REFCLK input (see Figure 83).
DATA RATE MODE SYNCHRONIZATION
The Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock section outlines the steps
required to synchronize multiple devices in data rate mode. The
procedure assumes that the DACCLK and REFCLK signals are
applied to all the devices. The following procedure must be
carried out on each individual device.
Procedure for Data Rate Synchronization When Directly
Sourcing the DAC Sampling Clock
Configure the AD9122 for data rate, periodic synchronization
by writing 0xC8 to the sync control register (Register 0x10).
Additional synchronization options are available (see the
Additional Synchronization Features section).
Read the sync locked bit (Register 0x12, Bit 6) to verify that the
device is back-end synchronized. A high level on this bit indicates
that the clocks are running with a constant and known phase
relative to the synchronization signal.
Reset the FIFO by strobing the FRAME signal high for one
complete DCI period. Resetting the FIFO ensures that the
correct data is being read from the FIFO of each of the devices
simultaneously.
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
DCIP/
DCIN
DACCLKP/
DACCLKN
REFCLKP/
REFCLKN
FRAMEP/
FRAMEN
DCIP/
DCIN
IOUT1P/
IOUT1N
IOUT2P/
IOUT2N
AD9122