AD9122 Analog Devices, AD9122 Datasheet - Page 55

• Manufacturer Part Number: AD9122
• Manufacturer: Analog Devices

Specifications of AD9122

• Resolution (bits): 16bit
• Dac Update Rate: 1.23GSPS
• Dac Settling Time: n/a
• Max Pos Supply (v): +3.47V
• Single-supply: No
• Dac Type: Current Out
• Dac Input Format: LVDS,Par

Figure 86 shows the synchronization signal timing with 2×
interpolation; therefore, f
shown to be equal to the FIFO rate. The maximum frequency
at which the device can be resynchronized in FIFO rate mode
can be expressed as
where N is any non-negative integer.
ADDITIONAL SYNCHRONIZATION FEATURES
Table 26 shows the required timing between the DACCLK and the
synchronization clock when synchronization is used. This timing
restriction applies to both data rate mode and FIFO rate mode.
Table 26. Synchronization Setup and Hold Times
Parameter
t
t
t
One-Time Synchronization
When implementing the full multichip synchronization feature
(with the REFCLK and FRAME signals aligned within one DACCLK
cycle), the user may experience difficulty meeting the DACCLK to
synchronization clock timing. In this case, a one-time synchroni-
zation method can be used. Before implementing the one-time
synchronization, make sure that the synchronization signal is
locked by checking both the sync signal locked and the sync signal
lost flags (Bit 4 and Bit 5 in Register 0x06). It is also important
that synchronization not be enabled before stable REFCLK signals
are present from the FPGA or ASIC. For more information and
a detailed flowchart of the one-time synchronization feature, see
the
AD9122 TxDAC+ Converters. ”
Sync Status Bits
When the sync locked bit (Register 0x12, Bit 6) is set, it indicates
that the synchronization logic has reached alignment. This align-
ment is determined when the clock generation state machine
phase is constant.
Alignment takes from (11 + averaging) × 64 to (11 + averaging) ×
128 DACCLK cycles. The sync locked bit can also trigger an IRQ ,
as described in the
When the sync lost bit (Register 0x12, Bit 7) is set, it indicates
that a previously synchronized device has lost alignment. This
bit is latched and remains set until cleared by overwriting the
register. This bit can also trigger an IRQ , as described in the
Interrupt Request Operation
SKEW
SUSYNC
HSYNC
AN-1093
f
SYNC_I
= f
DATA
Application Note, “Synchronization of Multiple
/(8 × 2
Interrupt Request Operation
Min
−t
100
330
DACCLK
N
)
DCI
/2
= ½ × f
section.
CLK
Max
+t
. The REFCLK input is
DACCLK
/2
section.
Unit
ps
ps
ps
Rev. B | Page 55 of 60
The sync phase readback bits (Register 0x13, Bits[7:0]) report
the current clock phase in a 6.2 format. Bits[7:2] report which of
the 64 states (0 to 63) the clock is currently in. When averaging
is enabled, Bits[1:0] provide ¼ state accuracy (for 0, ¼, ½, ¾).
The lower two bits give an indication of the timing margin
issues that may exist. If the synchronization sampling is error
free, the fractional clock state should be 00.
Timing Optimization
The synchronization signal (REFCLK) is sampled by a version
of the DACCLK. If sampling errors are detected, the opposite
sampling edge can be selected to improve the sampling point.
The sampling edge can be selected by setting Register 0x10,
Bit 3 (1 = rising and 0 = falling).
The synchronization logic resynchronizes when a phase change
between the synchronization signal (REFCLK) and the state of the
clock generation state machine exceeds a threshold. To mitigate
the effects of jitter and prevent erroneous resynchronizations, the
relative phase can be averaged. The amount of averaging is set
by the sync averaging bits (Register 0x10, Bits[2:0]) and can be
set from 1 to 128. The higher the number of averages, the more
slowly the device recognizes and resynchronizes to a legitimate
phase correction. Generally, the averaging should be made as
large as possible while still meeting the allotted resynchroniza-
tion time interval. Note that, if the average synchronization
sampling result is in approximately the middle of the probability
curve, the synchronization engine can be unstable, resulting in
corrupted output.
The value of the Sync Phase Request[5:0] bits (Register 0x11,
Bits[5:0]) is the state to which the clock generation state machine
resets upon initialization. By varying this value, the timing of
the internal clocks, with respect to the synchronization signal
(REFCLK), can be adjusted. Every increment of the Sync Phase
Request[5:0] value advances the internal clocks by one DACCLK
cycle. This offset can be used for two purposes: to skew the out-
puts of two synchronized DAC outputs in increments of the
DACCLK cycle, and to change the relative timing between the
DAC output and the SYNC input (REFCLK). This may allow
for a more optimal placement of the DCI sampling point in data
rate synchronization mode.
AD9122