ADP5589 Analog Devices, ADP5589 Datasheet

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... I/Os required through interface connectors for front panel designs. The ADP5589, which handles all key scanning and decoding, can flag the main processor via an interrupt line when new key events have occurred. In addition, GPI changes and logic changes can be tracked as events via the FIFO, eliminating the Rev ...

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... ADP5589 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 Thermal Resistance ...................................................................... 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 Quick Device Overview................................................................... 7 Device Enable................................................................................ 8 Device Overview .......................................................................... 8 Detailed Description ........................................................................ 9 REVISION HISTORY 8/11—Revision A: Initial Version   Event FIFO .....................................................................................9   ...

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... Source current = OH-Leak SINK SINK V OH-Leak OSC FREQ f SCL t HIGH t LOW t SU; DAT t HD; DAT t SU; STA Rev Page ADP5589 Min Typ Max Unit 1.65 3.6 V 1.2 1.3 V 1.4 1 μ μ μ μ μ μ ...

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... ADP5589 Parameter Hold Time for Start/Repeated Start Bus Free Time for Stop and Start Condition Setup Time for Stop Condition Data Valid Time Data Valid Acknowledge Rise Time for SCL and SDA Fall Time for SCL and SDA Pulse Width of Suppressed Spike ...

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... JA soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance 24-Lead LFCSP Maximum Power Dissipation 1 25-Ball WLCSP Maximum Power Dissipation ESD CAUTION ), using the following JA Rev Page ADP5589 θ Unit JA 43.83 C/W 120 mW 43 C/W 120 mW ...

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... ADP5589 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP5589 TOP VIEW (Not to Scale) Figure 3. LFCSP Pin Configuration Table 4. Pin Function Descriptions Pin No. Pin No. (LFCSP) (WLCSP) Mnemonic Description GPIO 8. This pin functions as Row 7 if used as keypad. GPIO 7. This pin functions as Row 6 if used as keypad. ...

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... GPIO 19 (R1) LA1 (R2) LB1 LOGIC 1 (R3) LC1 (R0) LY1 (C8) LA2 (C7) LB2 LOGIC 2 (C6) LC2 (C9) LY2 (C6) CLK_IN CLK DIV (R3) CLK_OUT PWM_IN (C6) PWM (R3) PWM_OUT RESET1 (R4) RESET1 GEN RST RESET2 (C4) RESET2 GEN Figure 5. Internal Block Diagram Rev Page GND INT FIFO UPDATE REGISTERS ADP5589 ...

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... Configuration of the device is carried out by programming an array of internal registers via the I device status and pending interrupts can be flagged to an external processor via the INT pin. The ADP5589 options that are available for each model of the ADP5589. Table 5. Available Options Models ADP5589ACPZ-00-R7 ADP5589ACBZ-00-R7 ADP5589ACPZ-01-R7 ...

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... NMOS current sink. Rev Page KEY 3 PRESSED KEY 3 RELEASED GPI 7 ACTIVE SECOND KEY 3 RELEASED READ GPI 7 ACTIVE THIRD GPI 7 ACTIVE READ Figure 8. FIFO Operation ADP5589 can be program transaction transaction has completed. ADP5589 ...

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... ADP5589 VDD KEY SCAN CONTROL × 3 KEYPAD MATRIX Figure 9. Simplified Key Scan Block Figure 9 shows a simplified representation of the key scan block using three row and three column pins connected to a small 3 × 3, nine-switch keypad matrix. When the key scanner is idle, the row pins are pulled high and the column pins are driven low ...

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... EVENT_INT cleared. When the key is finally released, EVENT_INT is asserted, the event counter incremented, and the FIFO updated with the release event information. Rev Page OVRFLOW_INT EC[4:0] FIFO UPDATE FIFO FIFO KEY 32 PRESS 1 32 KEY 32 RELEASE Figure 12. Press and Release Event ADP5589 2 ...

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... When the key scanner completes scanning, it normally detects Key 1 to Key 11 as being pressed; however, this unique condi- tion is decoded by the ADP5589, and Key Event 89 is assigned to it eight more key event assignments are possible, allowing the keypad size to extend up to 96. However, if one of the extended keys is pressed, none of the keys on that row is detectable ...

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... Blanking out additional key presses ensures that the NO processor is not unnecessarily interrupted until the unlock YES events occur. Figure 16 shows the unlock sequence when the interrupt mask timer is enabled. NO YES YES YES NO YES YES NO NO YES Rev Page ADP5589 features an interrupt mask timer, INT_MASK_ ...

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... ADP5589 SET EVENT_INT = 1 START MASK TIMER LOCK_STAT = 1 YES SET TIMER EXPIRED? EVENT_INT = 1 START MASK TIMER LOCK_STAT = 1 EVENT NO DETECTED? YES MASK TIMER ENABLED? YES NO YES MASK NO TIMER EXPIRED? YES SET TIMER EXPIRED? EVENT_INT = 1 START MASK TIMER LOCK_STAT = 0 Figure 16. Unlock Sequence Rev Page ...

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... See the Detailed Register Descriptions section for GPO configuration and usage. Rev Page GPI 6 GPI_STATUS_A[5] CLEARED BY READ GPI_INT Figure 18. Single GPI Example FIFO 1 101 1 105 1 113 0 113 0 105 101 0 Figure 19. Multiple GPI Lines Example ADP5589 CLEARED BY WRITE ‘1’ ...

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... ADP5589 LOGIC BLOCKS Several of the ADP5589 I/O lines can be used as inputs and outputs for implementing some common logic functions. The R1, R2, and R3 I/O pins can be used as inputs, and the R0 I/O pin can be used as an output for Logic Block 1. The C8, C7, and C6 I/O pins can be used as inputs, and the C9 I/O pin can be used as an output, for Logic Block 2 ...

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... LY2_INV IN_LB2 110 IN_LC2 111 SEL[2:0] LOGIC2_SEL (R3) PWM_OUT 0 OUT 1 SEL AND features a clock divider block that divides down CLK_DIV_EN CLK_DIV[4:0] CLK CLK_IN 0 DIVIDER OUT 1 SEL CLK_INV Figure 24. Clock Divider Block features two reset blocks that can generate reset ADP5589 CLK_OUT (R3) ...

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... ADP5589 RST_PASSTHRU_EN RESET_TRIGGER_TIME[2:0] RESET1_EVENT_A[7:0] KEY RESET1_EVENT_B[7:0] SCAN CONTROL RESET1_EVENT_C[7:0] RESET2_EVENT_A[7:0] RESET2_EVENT_B[7:0] GPI SCAN CONTROL LOGIC BLOCK CONTROL Figure 25. Reset Blocks The RESET1 signal uses I/O Pin R4 as its output. A pass- through mode allows the main RST pin to be output on the R4 pin also. ...

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... Figure 27 shows a typical write sequence for programming an internal register. The cycle begins with a start condition, followed by the hard coded 7-bit device address, which for the ADP5589 is 0x34, followed by the R/ W bit set to 0 for a write cycle. The ADP5589 acknowledges the address byte by pulling the data line low ...

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... DEVICE ADDRESS 0 0 8-BIT REGISTER POINTER ADP5589 ACK followed by the R/ acknowledges the address byte by pulling the data line low. The 8-bit data is then read. The address pointer is then incremented to read the next data byte, and the host continues to pull the data ...

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... Reserved GPI_EVENT_EN_A[7:0] GPI_EVENT_EN_B[7:0] Reserved GPI_INTERRUPT_EN_A[7:0] GPI_INTERRUPT_EN_B[7:0] Reserved DEBOUNCE_DIS_A[7:0] DEBOUNCE_DIS_B[7:0] Reserved GPO_DATA_OUT_A[7:0] GPO_DATA_OUT_B[7:0] Reserved GPO_OUT_MODE_A[7:0] GPO_OUT_MODE_B[7:0] Reserved GPIO_DIRECTION_A[7:0] GPIO_DIRECTION_B[7:0] Reserved Rev Page Bit 2 Bit 1 REV_ID OVRFLOW_ GPI_INT INT EC[4:0] GPI_INT_STAT_C[2:0] GPI_STATUS_C[2:0] RPULL_CONFIG_E[5:0] GPI_INT_LEVEL_C[2:0] GPI_EVENT_EN_C[2:0] GPI_INTERRUPT_EN_C[2:0] DEBOUNCE_DIS_C[2:0] GPO_DATA_OUT_C[2:0] GPO_OUT_MODE_C[2:0] GPIO_DIRECTION_C[2:0] ADP5589 Bit 0 EVENT_INT ...

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... ADP5589 Addr. R/W Bit 7 Bit 6 0x33 R/W UNLOCK1_ STATE 0x34 R/W UNLOCK2_ STATE 0x35 R/W EXT_LOCK_ STATE 0x36 R/W 0x37 R/W 0x38 R/W RESET1_ EVENT_A Level 0x39 R/W RESET2_ EVENT_B Level 0x3A R/W RESET1_ EVENT_B Level 0x3B R/W RESET1_ EVENT_B Level 0x3C R/W RESET1_ EVENT_B Level 0x3D R/W RESET2_POL RESET1_POL 0x3E R/W 0x3F R/W 0x40 ...

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... Logic Block output from (LY2) is high. Logic Block output from Logic Block 1 (LY1) is low output from Logic Block 1 (LY1) is high unlocked locked. Event count value. Indicates how many events are currently stored on the FIFO. Rev Page ADP5589 ...

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... ADP5589 FIFO_1 Register 0x03 Table 10. FIFO_1 Bit Descriptions Bits Name R/W 7 Event1_State R [6:0] EVENT1_IDENTIFIER[6:0] Table 11. Event Decoding Event No. Meaning Event No event 32 1 Key 1 (R0, C0 Key 2 (R0, C1 Key 3 (R0, C2 Key 4 (R0, C3 Key 5 (R0, C4 Key 6 (R0, C5 Key 7 (R0, C6) ...

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... Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Description Refer to Table 10. Refer to Table 10. Rev Page ADP5589 ...

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... ADP5589 FIFO_10 Register 0x0C Table 20. FIFO_10 Bit Descriptions Bits Name R/W 7 Event10_State R [6:0] EVENT10_IDENTIFIER[6:0] R FIFO_11 Register 0x0D Table 21. FIFO_11 Bit Descriptions Bits Name R/W 7 Event11_State R [6:0] EVENT11_IDENTIFIER[6:0] R FIFO_12 Register 0x0E Table 22. FIFO_12 Bit Descriptions Bits Name R/W 7 Event12_State R [6:0] EVENT12_IDENTIFIER[6:0] R FIFO_13 Register 0x0F Table 23. FIFO_13 Bit Descriptions ...

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... GPI_10 (C1 pin). Cleared on read interrupt interrupt due to GPI_9 (C0 pin). Cleared on read. Description Reserved interrupt interrupt due to GPI_19 (C10 pin). Cleared on read interrupt interrupt due to GPI_18 (C9 pin). Cleared on read interrupt interrupt due to GPI_17 (C8 pin). Cleared on read. Rev Page ADP5589 ...

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... ADP5589 GPI_STATUS_A Register 0x16 Table 30. GPI_STATUS_A Bit Descriptions Bits Name R/W 7 GPI_8_STAT R 6 GPI_7_STAT R 5 GPI_6_STAT R 4 GPI_5_STAT R 3 GPI_4_STAT R 2 GPI_3_STAT R 1 GPI_2_STAT R 0 GPI_1_STAT R GPI_STATUS_B Register 0x17 Table 31. GPI_STATUS_B Bit Descriptions Bits Name R/W 7 GPI_16_STAT R 6 GPI_15_STAT R 5 GPI_14_STAT R 4 GPI_13_STAT ...

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... Rev Page ADP5589 ...

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... ADP5589 RPULL_CONFIG_C Register 0x1B Table 35. RPULL_CONFIG_C Bit Descriptions Bits Name R/W [7 :6] C3_PULL_CFG R/W [5: 4] C2_PULL_CFG R/W [3: 2] C1_PULL_CFG R/W [1: 0] C0_PULL_CFG R/W RPULL_CONFIG_D Register 0x1C Table 36. RPULL_CONFIG_D Bit Descriptions Bits Name R/W [7: 6] C7_PULL_CFG R/W [5:4] C6_PULL_CFG R/W [3: 2] C5_PULL_CFG R/W [1: 0] C4_PULL_CFG R/W RPULL_CONFIG_E Register 0x1D Table 37. RPULL_CONFIG_E Bit Descriptions ...

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... GPI_10 interrupt is active high GPI_9 interrupt is active low GPI_9 interrupt is active high. Description Reserved GPI_19 interrupt is active low GPI_19 interrupt is active high GPI_18 interrupt is active low GPI_18 interrupt is active high GPI_17 interrupt is active low GPI_17 interrupt is active high. Rev Page ADP5589 ...

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... ADP5589 GPI_EVENT_EN_A Register 0x21 Table 41. GPI_EVENT_EN_A Bit Descriptions Bits Name R/W 7 GPI_8_EVENT_EN R/W 6 GPI_7_EVENT_EN R/W 5 GPI_6_EVENT_EN R/W 4 GPI_5_EVENT_EN R/W 3 GPI_4_EVENT_EN R/W 2 GPI_3_EVENT_EN R/W 1 GPI_2_EVENT_EN R/W 0 GPI_1_EVENT_EN R/W GPI_EVENT_EN_B Register 0x22 Table 42. GPI_EVENT_EN_B Bit Descriptions Bits Name R/W 7 GPI_16_EVENT_EN R/W 6 GPI_15_EVENT_EN R/W 5 GPI_14_EVENT_EN R/W 4 GPI_13_EVENT_EN R/W 3 GPI_12_EVENT_EN R/W 2 GPI_11_EVENT_EN R/W 1 GPI_10_EVENT_EN R/W 0 GPI_9_EVENT_EN R/W GPI_EVENT_EN_C Register 0x23 Table 43. GPI_EVENT_EN_C Bit Descriptions ...

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... GPI_10_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_10_INT is set and the GPI interrupt condition is met GPI_9_INT is disabled GPI_9_INT enable. Assert the GPI_INT bit (Register 0x01, Bit 1) if GPI_9_INT is set and the GPI interrupt condition is met. Rev Page ADP5589 ...

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... ADP5589 GPI_INTERRUPT_EN_C Register 0x26 Table 46. GPI_INTERRUPT_EN_C Bit Descriptions Bits Name R/W [ GPI_19_INT_EN R/W 1 GPI_18_INT_EN R/W 0 GPI_17_INT_EN R/W DEBOUNCE_DIS_A Register 0x27 Table 47. DEBOUNCE_DIS_A Bit Descriptions Bits Name R/W 7 GPI_8_DEB_DIS R/W 6 GPI_7_DEB_DIS R/W 5 GPI_6_DEB_DIS R/W 4 GPI_5_DEB_DIS R/W 3 GPI_4_DEB_DIS R/W 2 GPI_3_DEB_DIS R/W 1 GPI_2_DEB_DIS R/W 0 GPI_1_DEB_DIS R/W DEBOUNCE_DIS_B Register 0x28 Table 48. DEBOUNCE_DIS_B Bit Descriptions Bits Name R/W 7 GPI_16_DEB_DIS ...

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... GPI 17. Description 0 = low high low high low high low high low high low high low high low high. Description 0 = low high low high low high low high low high low high low high low high. Rev Page ADP5589 ...

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... ADP5589 GPO_DATA_OUT_C Register 0x2C Table 52. GPO_DATA_OUT_C Bit Descriptions Bits Name R/W [ GPO_19_DATA R/W 1 GPO_18_DATA R/W 0 GPO_17_DATA R/W GPO_OUT_MODE_A Register 0x2D Table 53. GPO_OUT_MODE_A Bit Descriptions Bits Name R/W 7 GPO_8_OUT_MODE R/W 6 GPO_7_OUT_MODE R/W 5 GPO_6_OUT_MODE R/W 4 GPO_5_OUT_MODE R/W 3 GPO_4_OUT_MODE R/W 2 GPO_3_OUT_MODE R/W 1 GPO_2_OUT_MODE R/W 0 GPO_1_OUT_MODE R/W GPO_OUT_MODE_B Register 0x2E Table 54. GPO_OUT_MODE_B Bit Descriptions Bits Name R/W 7 GPO_16_OUT_MODE ...

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... GPIO output GPIO input GPIO output GPIO input GPIO output GPIO input GPIO output GPIO input GPIO output GPIO input GPIO output GPIO input GPIO output. Rev Page ADP5589 ...

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... ADP5589 GPIO_DIRECTION_C Register 0x32 Table 58. GPIO_DIRECTION_C Bit Descriptions Bits Name R/W [7:3] 2 GPIO_19_DIR R/W 1 GPIO_18_DIR R/W 0 GPIO_17_DIR R/W UNLOCK1 Register 0x33 Table 59. UNLOCK1 Bit Descriptions Bits Name R/W 7 UNLOCK1_STATE R/W [6:0] UNLOCK1[6:0] R/W UNLOCK2 Register 0x34 Table 60. UNLOCK2 Bit Descriptions Bits Name R/W 7 UNLOCK2_STATE R/W [6:0] UNLOCK2[6:0] R/W EXT_LOCK_EVENT Register 0x35 Table 61. EXT_LOCK_EVENT Bit Descriptions ...

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... If one of the registers is 0, that register is not used for reset generation. All reset events must be detected at the same time to trigger the reset. R/W Description R/W Defines which level the second reset event should be. R/W Defines an event that can be used to generate the RESET1 signal. Rev Page ADP5589 ...

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... ADP5589 RESET1_EVENT_C Register 0x3A Table 66. RESET1_EVENT_C Bit Descriptions Bits Name 7 RESET1_EVENT_B Level [6: 0] RESET1_EVENT_C[6:0] RESET2_EVENT_A Register 0x3B Table 67. RESET2_EVENT_A Bit Descriptions Bits Name 7 RESET1_EVENT_B Level [6:0] RESET2_EVENT_A[6:0] RESET2_EVENT_B Register 0x3C Table 68. RESET2_EVENT_B Bit Descriptions Bits Name 7 RESET1_EVENT_B Level [6:0] RESET2_EVENT_B[6:0] RESET_CFG Register 0x3D Table 69 ...

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... AND the internally generated PWM signal with an externally supplied PWM signal (C6). R/W Defines PWM mode continuous one shot one-shot is performed, the PWM_EN bit is automatically cleared second one-shot must be performed, the user must set PWM_EN again. R/W Enable PWM generator. Rev Page ADP5589 ...

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... ADP5589 CLOCK_DIV_CFG Register 0x43 Table 75. CLOCK_DIV_CFG Bit Descriptions Bits Name 7 6 CLK_INV [5: 1] CLK_DIV[4:0] 0 CLK_DIV_EN LOGIC_1_CFG Register 0x44 Table 76. LOGIC_1_CFG Bit Descriptions Bits Name 7 6 LY1_INV 5 LC1_INV 4 LB1_INV 3 LA1_INV [2: 0] LOGIC1_SEL[2:0] LOGIC_2_CFG Register 0x45 Table 77. LOGIC_2_CFG Bit Descriptions Bits Name R/W 7 LY1_CASCADE ...

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... LY1 cannot generate interrupt allow LY1 activity to generate events on the FIFO. Configure the logic level of LY1 that generates an interrupt LY1 is active low LY1 is active high. Description Reserved. Configure time between consecutive scan cycles ms. Rev Page ADP5589 ...

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... ADP5589 PIN_CONFIG_A Register 0x49 Table 81. PIN_CONFIG_A Bit Descriptions Bits Name R/W 7 R7_CONFIG R/W 6 R6_CONFIG R/W 5 R5_CONFIG R/W 4 R4_CONFIG R/W 3 R3_CONFIG R/W 2 R2_CONFIG R/W 1 R1_CONFIG R/W 0 R0_CONFIG R/W PIN_CONFIG_B Register 0x4A Table 82. PIN_CONFIG_B Bit Descriptions Bits Name R/W 7 C7_CONFIG R/W 6 C6_CONFIG R/W 5 C5_CONFIG R/W 4 C4_CONFIG R/W 3 C3_CONFIG R/W 2 C2_CONFIG R/W 1 C1_CONFIG R/W 0 C0_CONFIG R/W PIN_CONFIG_C Register 0x4B Table 83. PIN_CONFIG_C Bit Descriptions ...

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... Configure the behavior of the INT pin if the user tries to clear it while an interrupt is pending INT pin remains asserted if an interrupt is pending INT pin deasserts for 50 μs and reasserts if an interrupt is pending. Configure the response ADP5589 has to the RST pin ADP5589 resets if RST is low ADP5589 does not reset if RST is low. Rev Page ADP5589 ...

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... ADP5589 INT_EN Register 0x4E Table 86. INT_EN Bit Descriptions Bits Name R/W [ LOGIC2_IEN R/W 4 LOGIC1_IEN R/W 3 LOCK_IEN R/W 2 OVRFLOW_IEN R/W 1 GPI_IEN R/W 0 EVENT_IEN R/W Description Reserved Logic 2 interrupt is disabled assert the INT pin if LOGIC2_INT is set Logic 1 interrupt is disabled assert the INT pin if LOGIC1_INT is set lock interrupt is disabled assert the INT pin if LOCK_INT is set. ...

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... Figure 31. Typical Configuration Rev Page VDD SDA SCL RST VDD ADP5589 UVLO OSCILLATOR POR INTERFACE KEY SCAN AND DECODE GPI SCAN AND DECODE LOGIC1 I/O LOGIC2 REGISTERS CONFIG CLK DIV PWM RESET1 GEN RESET2 GEN GND ADP5589 INT ...

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... Temperature Range ADP5589ACPZ-00-R7 −40°C to +85°C ADP5589ACPZ-01-R7 −40°C to +85°C ADP5589ACPZ-02-R7 −40°C to +85°C ADP5589ACBZ-00-R7 −40°C to +85°C ADP5589ACBZ-01-R7 −40°C to +85°C ADP5589ACBZ-02-R7 −40°C to +85°C ADP5589CP-EVALZ RoHS Compliant Part refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ...