ADP5589 Analog Devices, ADP5589 Datasheet - Page 17

• Manufacturer Part Number: ADP5589
• Description: Keypad Decoder and I/O Expansion
• Manufacturer: Analog Devices

Specifications of ADP5589

• Vin Range: 1.8 to 3.0V
• Number Of I/os: 19
• Application: Mobil I-0 Exp-Keybd Cont,Mobil I-O Expander
• Qwerty Keypad: Yes
• Other Functions: I2C I/O & register
• Function Flag: Mobil I-O
• Package: 24-Lead LFCSP,25-Ball WLCSP

PWM BLOCK
The
configured to drive out on I/O Pin R3. PWM on/off times are
programmed via four 8-bit registers.
Newly programmed values are not latched until the final byte,
PWM_ONT_HIGH_BYTE (Address 0x41, Bits[7:0]), is written
to (see Figure 23).
The highest frequency obtainable from the PWM is performed
by setting the least significant bit (LSB) of both the on and off
bit patterns, resulting in a 500 kHz signal with a 50% duty cycle.
Each LSB respresents 1 μs of on or off time.
The PWM block provides support for continuous PWM
mode as well as a one-shot mode (see Table 74). Additionally,
an external signal can be AND’ e d with the internal PWM signal.
This option can be selected by writing a 1 to PWM_IN_AND,
PWM_CFG[2]. The input to the external AND is the C6 I/O
pin. C6 should be set to GPI (GPIO15). Note that the debounce
for C6 will result in a delay of the AND’ing, and can be
controlled using register GPI_15_DEB_DIS (Address 0x28,
Bit[6]).
Newly programmed values are not latched until the final byte,
PWM_ONT_HIGH_BYTE (Address 0x41, Bits[7:0]), is written.
ADP5589
features a PWM generator whose output can be
LA2
LY1
LY1_CASCADE
PWM_EN
PWM_MODE
PWM_OFFT_LOW_BYTE[7:0]
PWM_OFFT_HIGH_BYTE[7:0]
PWM_ONT_LOW_BYTE[7:0]
PWM_ONT_HIGH_BYTE[7:0]
(C6) PWM_IN
PWM_IN_AND
0
1
SEL
LC2
OUT
LB2
C6_EXTEND_CFG = 1
(LY1)
(LY1)
LC2
LC2
LB2
LB2
LA2
LA2
LC2_INV
LB2_INV
LA2_INV
0
1
0
1
0
1
SEL
SEL
SEL
OUT
OUT
OUT
IN_LC2
IN_LB2
(IN_LY1)
IN_LA2
(IN_LY1)
(IN_LY1)
(IN_LY1)
IN_LA2
IN_LB2
IN_LC2
IN_LA2
IN_LB2
IN_LC2
IN_LA2
IN_LB2
IN_LC2
IN_LA2
IN_LB2
IN_LC2
OFF TIME[15:0]
FF2_CLR
ON TIME[15:0]
Figure 23. PWM Block Diagram
Figure 22. Logic Block 2
XOR
AND
OR
Rev. A | Page 17 of 48
FF2_SET
0
1
SEL
OUT
XOR
AND
OR
GENERATOR
0
1
0
1
0
1
D
SEL
SEL
SEL
SET
CLR
PWM
CLOCK DIVIDER BLOCK
The
the frequency of an externally supplied source via I/O Pin C6.
The output of the divider is driven out on I/O Pin R3.
RESET BLOCKS
The
conditions if certain events are detected at the same time. Up to
three reset trigger events can be programmed for RESET1. Up
to two reset trigger events can be programmed for RESET2. The
event scan control blocks monitor whether these events are present
for the duration of RESET_TRIGGER_TIME[2:0] (0x3D[4:2]).
If they are, reset-initiate signals are sent to the reset generator
blocks. The generated reset signal pulse width is programmable.
OUT
OUT
OUT
Q
(C6)
AND2
OR2
XOR2
FF2
ADP5589
ADP5589
CLK_DIV[4:0]
CLK_IN
CLK_INV
CLK_DIV_EN
IN_LA2
IN_LB2
IN_LC2
AND2
XOR2
AND
GND
OR2
FF2
features a clock divider block that divides down
features two reset blocks that can generate reset
LOGIC2_SEL
000
001
010
011
100
101
110
111
SEL[2:0]
MUX
0
1
OUT
Figure 24. Clock Divider Block
SEL
OUT
DIVIDER
CLK
(R3)
PWM_OUT
LY2
LY2
LY2_INV
0
1
SEL
OUT
LY2
0
1
SEL
OUT
CLK_OUT
ADP5589
(R3)