LPC1850FET256 NXP Semiconductors, LPC1850FET256 Datasheet - Page 57

The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2

LPC1850FET256

Manufacturer Part Number
LPC1850FET256
Description
The LPC1850FET256 is a high-performance, cost-effective Cortex-M3 microcontroller featuring 200 kB of SRAM, and advanced peripherals including Ethernet, High Speed USB 2
Manufacturer
NXP Semiconductors
Datasheet

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Table 3.
LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See
LPC1850_30_20_10
Preliminary data sheet
Symbol
PE_14
PE_15
PF_0
PF_1
Pin description
C15
E13
D12
E11
-
-
-
-
…continued
-
-
-
-
-
-
-
159 -
All information provided in this document is subject to legal disclaimers.
-
-
-
Rev. 3.1 — 15 December 2011
-
-
-
-
[3]
[3]
[3]
[3]
I; PU -
I; PU -
O;
PU
I; PU -
-
-
O
I/O GPIO7[14] — General purpose digital input/output
-
-
-
O
I/O I2C1_SCL — I
O
I/O GPIO7[15] — General purpose digital input/output
-
-
-
I/O SSP0_SCK — Serial clock for SSP0.
I
-
-
-
-
-
O
-
I/O SSP0_SSEL — Slave Select for SSP0.
-
I/O GPIO7[16] — General purpose digital input/output
-
-
-
Description
R — Function reserved.
R — Function reserved.
R — Function reserved.
EMC_DYCS3 — SDRAM chip select 3.
pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
CTOUT_0 — SCT output 0. Match output 0 of
timer 0.
not use a specialized I
EMC_CKEOUT3 — SDRAM clock enable 3.
pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
GP_CLKIN — General purpose clock input to the
CGU.
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
R — Function reserved.
I2S1_TX_MCLK — I
R — Function reserved.
R — Function reserved.
R — Function reserved.
pin.
R — Function reserved.
R — Function reserved.
R — Function reserved.
Table
32-bit ARM Cortex-M3 microcontroller
LPC1850/30/20/10
2.
2
C1 clock input/output (this pin does
2
S1 transmit master clock.
2
C pad).
© NXP B.V. 2011. All rights reserved.
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