STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 132

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

General-purpose timers
10.1.7
10.1.8
132/232
Forced output mode
In output mode (CCyS bits = 00 in the TIMx_CCMR1 register), software can force each
output compare signal (OCyREF and then OCy) to an active or inactive level independently
of any comparison between the output compare register and the counter.
To force an output compare signal (OCyREF/OCy) to its active level, write 101 in the
TIM_OCyM bits in the corresponding TIMx_CCMR1 register. OCyREF is forced high
(OCyREF is always active high) and OCy gets the opposite value to the TIM_CCyP polarity
bit. For example, TIM_CCyP = 0 defines OCy as active high, so when OCyREF is active,
OCy is also set to a high level.
The OCyREF signal can be forced low by writing the TIM_OCyM bits to 100 in the
TIMx_CCMR1 register.
The comparison between the TIMx_CCRy shadow register and the counter is still performed
and allows the INT_TIMxCCRyIF flag to be set. Interrupt requests can be sent accordingly.
This is described in
Output compare mode
This mode is used to control an output waveform or to indicate when a period of time has
elapsed.
When a match is found between the capture/compare register and the counter, the output
compare function:
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●
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The TIMx_CCRy registers can be programmed with or without buffer registers using the
TIM_OCyBE bit in the TIMx_CCMR1 register.
In output compare mode, the update event has no effect on OCyREF or the OCy output.
The timing resolution is one count of the counter. Output compare mode can also be used to
output a single pulse (in one pulse mode).
Procedure:
1.
2.
3.
4.
5.
Assigns the corresponding output pin to a programmable value defined by the output
compare mode (the TIM_OCyM bits in the TIMx_CCMR1 register) and the output
polarity (the TIM_CCyP bit in the TIMx_CCER register). The output can remain
unchanged (TIM_OCyM = 000), be set active (TIM_OCyM = 001), be set inactive
(TIM_OCyM = 010), or can toggle (TIM_OCyM = 011) on the match.
Sets a flag in the interrupt flag register (the INT_TIMCCyIF bit in the INT_TIMxFLAG
register).
Generates an interrupt if the corresponding interrupt mask is set (the TIM_CCyIF bit in
the INT_TIMxCFG register).
Select the counter clock (internal, external, and prescaler).
Write the desired data in the TIMx_ARR and TIMx_CCRy registers.
Set the INT_TIMCCyIF bit in INT_TIMxCFG if an interrupt request is to be generated.
Select the output mode. For example, you must write TIM_OCyM = 011, TIM_OCyBE =
0, TIM_CCyP = 0 and TIM_CCyE = 1 to toggle the OCy output pin when TIMx_CNT
matches TIMx_CCRy, TIMx_CCRy buffer is not used, OCy is enabled and active high.
Enable the counter by setting the TIM_CEN bit in the TIMx_CR1 register.
Section 10.1.8: Output compare mode on page
STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
Doc ID 16252 Rev 13
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