STM32W108CZ STMicroelectronics, STM32W108CZ Datasheet - Page 179

• Manufacturer Part Number: STM32W108CZ
• Description: High-performance, IEEE 802.15.4 wireless system-on-chip with embedded Flash memory
• Manufacturer: STMicroelectronics

Specifications of STM32W108CZ

• Receive Current (w/ Cpu): 27 mA
• Transmit Current (w/ Cpu, +3 Dbm Tx): 31 mA
• Low Deep Sleep Current, With Retained Ram And Gpio: 400 nA/800 nA with/without sleep timer
• Standard Arm Debug Capabilities: Flash patch & breakpoint; data watchpoint & trace; instrumentation trace macrocell
• Single Voltage Operation: 2.1-3.6 V with internal 1.8 V and 1.25 V regulators

STM32W108HB STM32W108CC STM32W108CB STM32W108CZ
11.2
Note:
Equation notes
●
●
●
●
Interrupts
The ADC has its own ARM
ADC interrupt is enabled by writing the INT_ADC bit to the INT_CFGSET register, and
cleared by writing the INT_ADC bit to the INT_CFGCLR register.
page 186
Four kinds of ADC events can generate an ADC interrupt, and each has a bit flag in the
INT_ADCFLAG register to identify the reason(s) for the interrupt:
●
●
●
●
Bits in INT_ADCFLAG may be cleared by writing a 1 to their position.
The INT_ADCCFG register controls whether or not INT_ADCFLAG bits actually request the
ARM
so.
For non-interrupt (polled) ADC operation set INT_ADCCFG to zero, and read the bit flags in
INT_ADCFLAG to determine the ADC status.
When making changes to the ADC configuration it is best to disable the DMA beforehand. If
this isn’t done it can be difficult to determine at which point the sample data in the DMA
buffer switch from the old configuration to the new configuration. However, since the ADC
will be left running, if it completes a conversion after the DMA is disabled, the INT_ADCOVF
flag will be set. To prevent these unwanted DMA buffer overflow indications, clear the
INT_ADCOVF flag immediately after enabling the DMA, preferably with interrupts off.
Disabling the ADC in addition to the DMA is often undesirable because of the additional
analog startup time when it is re-enabled.
All N are 16-bit two’s complement numbers.
N
the minimum two’s complement value 0x8000 as the conversion result. Instead, VGND
yields a two’s complement value close to 0xE000 when the input buffer is not selected.
VGND cannot be measured when the input buffer is enabled because it is outside the
buffer’s input range.
N
the maximum positive two’s complement 0x7FFF as the conversion result. Instead,
VREF yields a two’s complement value close to 0x2000 when the input buffer is not
selected and yields a two’s complement value close to 0xF000 when the input buffer is
selected.
Offset correction is affected by the gain correction value. Offset correction is calculated
after gain correction has been applied.
INT_ADCOVF – an ADC conversion result was ready but the DMA was disabled (DMA
buffer overflow).
INT_ADCSAT– the gain correction multiplication exceeded the limits for a signed 16-bit
number (gain saturation).
INT_ADCULDFULL – the DMA wrote to the last location in the buffer (DMA buffer full).
INT_ADCULDHALF – the DMA wrote to the last location of the first half of the DMA
buffer (DMA buffer half full).
®
GND
VREF
Cortex-M3 ADC interrupt; only the events whose bits are 1 in INT_ADCCFG can do
describes the interrupt system in detail.
is a sampling of ground. Due to the ADC's internal design, VGND does not yield
is a sampling of VREF. Due to the ADC's internal design, VREF does not yield
®
Cortex-M3 vectored interrupt with programmable priority. The
Doc ID 16252 Rev 13
Analog-to-digital converter
Section 12: Interrupts on
179/232