ST72561R9 STMicroelectronics, ST72561R9 Datasheet - Page 196

• Manufacturer Part Number: ST72561R9
• Description: 8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
• Manufacturer: STMicroelectronics

Specifications of ST72561R9

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
beCAN CONTROLLER (Cont’d)
CAN ERROR STATUS REGISTER (CESR)
Read / Write
Reset Value: 0000 0000 (00h)
Bit 7 = Reserved. Forced to 0 by hardware.
Bits 6:4 = LEC[2:0] Last Error Code
- Read/Set/Clear
This field holds a code which indicates the type of
the last error detected on the CAN bus. If a mes-
sage has been transferred (reception or transmis-
sion) without error, this field will be cleared to ‘0’.
The code 7 is unused and may be written by the
CPU to check for update
Table 30. LEC Error Types
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = BOFF Bus-Off Flag
- Read
This bit is set by hardware when it enters the bus-
off state. The bus-off state is entered on TECR
overrun, TEC greater than 255, refer to section
0.1.4.5 on page 14.
Bit 1 = EPVF Error Passive Flag
- Read
This bit is set by hardware when the Error Passive
limit has been reached (Receive Error Counter or
Transmit Error Counter greater than 127).
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7
0
Code
0
1
2
3
4
5
6
7
LEC2
No Error
Stuff Error
Form Error
Acknowledgment Error
Bit recessive Error
Bit dominant Error
CRC Error
Set by software
LEC1
LEC0
Error Type
0
BOFF EPVF EWGF
0
Bit 1 = EWGF Error Warning Flag
- Read
This bit is set by hardware when the warning limit
has been reached. Receive Error Counter or
Transmit Error Counter greater than 96.
CAN ERROR INTERRUPT ENABLE REGISTER
(CEIER)
All bits of this register are set and clear by soft-
ware.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = ERRIE Error Interrupt Enable
0: No interrupt will be generated when an error
1: An interrupt will be generation when an error
Bits 6:5 = Reserved. Forced to 0 by hardware.
Bit 4 = LECIE Last Error Code Interrupt Enable
0: ERRI bit will not be set when the error code in
1: ERRI bit will be set when the error code in
Bit 3 = Reserved. Forced to 0 by hardware.
Bit 2 = BOFIE Bus-Off Interrupt Enable
0: ERRI bit will not be set when BOFF is set.
1: ERRI bit will be set when BOFF is set.
Bit 1 = EPVIE Error Passive Interrupt Enable
0: ERRI bit will not be set when EPVF is set.
1: ERRI bit will be set when EPVF is set.
Bit 0 = EWGIE Error Warning Interrupt Enable
0: ERRI bit will not be set when EWGF is set.
1: ERRI bit will be set when EWGF is set.
ERRIE
condition is pending in the CESR.
condition is pending in the CESR.
LEC[2:0] is set by hardware on error detection.
LEC[2:0] is set by hardware on error detection.
7
0
0
LECIE
0
BOFIE EPVIE EWGIE
0