ST72561R9 STMicroelectronics, ST72561R9 Datasheet - Page 228

• Manufacturer Part Number: ST72561R9
• Description: 8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
• Manufacturer: STMicroelectronics

Specifications of ST72561R9

• Hdflash Endurance: 100 cycles, data retention 40 years at 85°C
• 5 Power Saving Modes: Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow

ST72561
CLOCK CHARACTERISTICS (Cont’d)
12.5.4 PLL Characteristics
Notes:
1. Data characterized but not tested.
2. Under characterization
Figure 123. PLL Jitter vs Signal Frequency
Notes:
1. Measurement conditions: f
228/265
Operating conditions: V
V
f
Δ f
OSC
DD(PLL)
Symbol
CPU
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
/f
CPU
2000
PLL Voltage Range
PLL input frequency range
PLL jitter
Application Signal Frequency (KHz)
1000
Parameter
1)
DD
CPU
500
3.8 to 5.5V @ T
= 4 MHz, T
250
PLL ON
PLL OFF
A
T
T
f
f
OSC
OSC
= 25°C
A
A
125
= 0 to +70
= -40 to +125
A
= 4 MHz, V
= 2 MHz, V
0 to 70°C
1)
Conditions
°
C
DD
DD
The user must take the PLL jitter into account in
the application (for example in serial communica-
tion or sampling of high frequency signals). The
PLL jitter is a periodic effect, which is integrated
over several CPU cycles. Therefore, the longer the
period of the application signal, the less it is im-
pacted by the PLL jitter.
Figure 123
plication signals in the range 125 kHz to 2 MHz. At
frequencies of less than 125 kHz, the jitter is neg-
ligible.
1)
°
C
or V
= 4.5 to 5.5V
= 4.5 to 5.5V
DD
4.5 to 5.5V @ T
shows the PLL jitter integrated on ap-
Min
3.8
4.5
2
A
Typ
-40 to 125°C
Note 2
Max
5.5
4
MHz
Unit
%