ST72561R9 STMicroelectronics, ST72561R9 Datasheet - Page 56

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ST72561R9

Manufacturer Part Number
ST72561R9
Description
8-BIT MCU WITH FLASH OR ROM, 10-BIT ADC, 5 TIMERS, SPI, LINSCI(TM), ACTIVE CAN
Manufacturer
STMicroelectronics
Datasheet

Specifications of ST72561R9

Hdflash Endurance
100 cycles, data retention 40 years at 85°C
5 Power Saving Modes
Halt, Auto Wake Up From Halt, Active Halt, Wait and Slow
ST72561
WINDOW WATCHDOG (Cont’d)
Figure 36. Exact Timeout Duration (t
56/265
WHERE:
t
t
t
CNT = Value of T[5:0] bits in the WDGCR register (6 bits)
MSB and LSB are values from the table below depending on the timebase selected by the TB[1:0] bits
in the MCCSR register
To calculate the minimum Watchdog Timeout (t
IF
To calculate the maximum Watchdog Timeout (t
IF
Note: In the above formulae, division results must be rounded down to the next integer value.
Example:
With 2ms timeout selected in MCCSR register
min0
max0
OSC2
(MCCSR Reg.)
WDGCR Register (Hex.)
Value of T[5:0] Bits in
CNT
CNT
TB1 Bit
= (LSB + 128) x 64 x t
= 16384 x t
= 125ns if f
0
0
1
1
<
MSB
-------------
MSB
-------------
00
3F
4
4
(MCCSR Reg.)
OSC2
OSC2
TB0 Bit
THEN
ELSE
THEN
ELSE
0
1
0
1
= 8 MHz
t
Min. Watchdog
t
max
t
min
Timeout (ms)
OSC2
t
max
min
1.496
=
=
t
Selected MCCSR
128
min
=
=
t
t
min0
max0
t
t
Timebase
min0
max0
10ms
25ms
2ms
4ms
min
+
+
+
+
and t
16384
16384
16384
16384
Max. Watchdog
Timeout (ms)
max
128.552
×
×
×
2.048
t
×
max
MSB
CNT
CNT
)
min
CNT
CNT
max
20
49
4
8
):
):
×
×
t
4CNT
---------------- -
LSB
MSB
t
osc2
4CNT
---------------- -
osc2
MSB
59
53
35
54
+
+
(
(
192
192
+
+
LSB
LSB
)
) 64
×
×
64
×
×
4CNT
---------------- -
MSB
4CNT
---------------- -
MSB
×
×
t
t
osc2
osc2

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