ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet

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... Auto Wakeup from Halt, Wait and Slow I/O Ports – multifunctional bidirectional I/Os – high sink outputs February 2008 ST7FOXF1, ST7FOXK1, ST7FOXK2 8-bit MCU with single voltage Flash memory, DIP20 6 timers – Configurable watchdog timer – Dual 8-bit Lite timers with prescaler, 1 real time base and 1 input capture – ...

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... RC oscillator adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.1.1 6.1.2 6.1.3 2/226 In-Circuit Programming (ICP Application Programming (IAP Read-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Flash write/erase protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Accumulator ( Index registers (X and Program Counter (PC Condition Code register (CC Stack Pointer (SP Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Customized RC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Auto wakeup RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 6.2 Multi-oscillator (MO 6.2.1 6.2.2 6.2.3 6.3 Reset sequence manager (RSM 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 System Integrity management (SI 6.4.1 6.5 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6.5.1 6.5.2 6.5.3 6.5.4 6.5.5 6.5.6 7 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 Masking and processing flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2.1 7.2.2 7.3 Interrupts and low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 7.4 Concurrent and nested management . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7.5 Description of interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 7.5.1 7.5.2 7.5.3 8 Power saving modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.2 Slow mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8 ...

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... AWUFH Control/Status Register (AWUCSR AWUFH prescaler register (AWUPR Input modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Analog alternate function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Standard ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Other ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Hardware watchdog option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 10.2.5 10.2.6 10.3 Lite timer 2 (LT2 110 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.4 16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10.4.1 10.4.2 10.4.3 10.4.4 10.4.5 10.4.6 10.4.7 10.4 bus interface (I 10.5.1 10.5.2 10.5.3 10.5.4 Slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 10.5.5 10.5.6 10.5.7 10.6 Serial peripheral interface (SPI 158 10.6.1 10.6.2 10.6.3 10.6.4 10.6.5 10.6.6 10.6.7 10.6.8 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Register description ...

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... Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Operating conditions with Low Voltage Detector (LVD 190 Internal RC oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 12.5 Communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . 194 12.5.1 12.5.2 12.6 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.6.1 12.6.2 12.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 12.8 EMC (electromagnetic compatibility) characteristics . . . . . . . . . . . . . . . 201 12.8.1 12.8.2 12.8.3 12.9 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.9.1 12.9.2 12.10 Control pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.10.1 Asynchronous RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.11 10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 13 Device configuration and ordering information . . . . . . . . . . . . . . . . . 211 13 ...

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... Interrupt software priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 14. Setting the interrupt software priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 15. Interrupt vector vs ISPRx bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 16. Dedicated interrupt instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Table 17. ST7FOXF1/ST7FOXK1 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 18. ST7FOXK2 interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 19. Interrupt sensitivity bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 20. Enabling/disabling active-halt and halt modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 21. Configuring the dividing factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 22 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 2 Table 49 register mapping and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Table 50. Low power mode descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 51. Interrupt events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Table 52. SPI Master mode SCK Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Table 53. SPI Register Map and Reset Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 Table 54. Effect of low power modes on the A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 Table 55 ...

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... List of tables Table 101. Thermal characteristics 224 Table 102. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 10/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

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... General block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 2. 32-pin SDIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 3. 32-pin LQFP 7x7 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 4. 20-pin SO and DIP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 5. ST7FOXF1/ST7FOXK1/ST7FOXK2 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 6. Typical ICC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 7. CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 8. Stack manipulation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Figure 9. RCCRH_USER and RCCRL_USER programming flowchart . . . . . . . . . . . . . . . . . . . . . . . 35 Figure 10 ...

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... Figure 91. Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Figure 92. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Figure 93. ST7FOXF1/ST7FOXK1/ST7FOXK2 ordering information scheme . . . . . . . . . . . . . . . . . 214 Figure 94. 20-pin plastic small outline package, 300-mil width, package outline 220 Figure 95. 20-pin plastic dual in-line package, 300-mil width, package outline . . . . . . . . . . . . . . . . . 221 Figure 96. ...

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... For a description of the DM registers, refer to the ST7 ICC Protocol Reference Manual. Table 1. Device summary Features Program memory - bytes RAM (stack) - bytes Timers ADC Peripherals Packages ST7FOXF1 / ST7FOXK1 4K 384 (128) Dual 8-bit timer, dual 12-bit AT (4 PWM 10-bit I²C DIP20, SO20, LQFP32, SDIP32 Description ST7FOXK2 8K ...

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... Int. 32 kHz RC OSC LVD Power Supply Control 8-bit core ALU Flash Program Memory ( Kbytes) RAM (384 bytes) ST7FOXF1, ST7FOXK1, ST7FOXK2 1) 16-bit timer 12-bit Auto-reload dual timer 8-bit dual Lite timer PA7:0 Port A (8 bits) PB7:0 Port B (8 bits) PC7:0 Port C ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 2 Pin description Figure 2. 32-pin SDIP package pinout OCMP1_A ATPWM2/MCO/PA4(HS) Note 1: Available on 8K version only Figure 3. 32-pin LQFP 7x7 package pinout ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ATPWM3/PA5(HS) I2CDATA/PA6(HS) I2CCLK/PA7(HS) BREAK1/PC7 1 ei2 1) /PA0(HS) 2 ei2 ATIC/PA1(HS) 3 ATPWM0/PA2(HS) 4 ATPWM1/PA3(HS) 5 ei0 6 ei2 ATPWM3/PA5(HS) 7 I2CDATA/PA6(HS) 8 I2CCLK/PA7(HS) 9 RESET ...

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... I ei0 ei0 I ST7FOXF1, ST7FOXK1, ST7FOXK2 Main function Alternate Output (after function reset) Port ATPWM1 (HS) Port A4 ATPWM2 (HS) MCO Port ATPWM3 (HS) Port A6 I2CDATA/SPI T (HS) serial clock I2CCLK/SPI Port A7 T ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 2. Device pin description (32-pin packages) (continued) Pin number Pin name 14 18 PB0/AIN0 15 19 PB1/AIN1/CLKIN 16 20 PB2/AIN2 ( PB3/AIN3/MOSI ( PB4/AIN4/MISO PB5/AIN5 (2) EXTCLK_A ( PB6/AIN6/SCK (2) PB7/AIN7/ (2) OCMP2_A PC0/AIN8 (2) ICAP1_A PC1/AIN9 (2) ICAP2_A 24 28 PC2/ICCDATA 25 29 ...

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... PA2 (HS)/ATPWM0 1. In the open-drain output column, T defines a true open-drain I/O (P-Buffer and protection diode to V implemented). 2. Available on ST7FOXK2 only mandatory to connect all available V 4. BREAK2 available on ST7FOXK2 only 5. Available on ST7FOXK1 only. Figure 4. 20-pin SO and DIP package pinout ATPWM0/PA2(HS) ATPWM1/PA3(HS) ATPWM2/MCO/PA4(HS) ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 3. Device pin description (20-pin package) Pin Pin Name Number 1 PC6 2 PA1 (HS)/ATIC 3 PA2 (HS)/ATPWM0 4 PA3 (HS)/ATPWM1 PA4 5 (HS)ATPWM2/MCO 6 PA5 (HS)ATPWM3 7 PA6 (HS)/I2CDATA 8 PA7 (HS)/ I2CCLK 9 RESET ( ( PB0/AIN0 13 PB1/AIN1/CLKIN 14 PB2/AIN2 15 PB3/AIN3 16 PB4/AIN4 17 PB5/AIN5 18 PC2/ICCDATA 19 PC3/ICCCLK ...

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... RAM (zero page) 00FFh 0100h RAM 017Fh 0180h 128 bytes Stack 01FFh Kbytes Flash program memory (4 Kbytes) (2 Kbytes) (1 Kbyte) 17) (0.5 Kbyte) ST7FOXF1, ST7FOXK1, ST7FOXK2 5) mapped in the upper part of the ST7 1000h RCCRH_USER 1001h RCCRL_USER DEE0h RCCRH DEE1h RCCRL see Section 6.1.1 E000h Sector 1 Sector 0 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 4. Hardware register map Address Block Register label 0000h PADR 0001h Port A PADDR 0002h PAOR 0003h PBDR 0004h Port B PBDDR 0005h PBOR 0006h PCDR 0007h Port C PCDDR 0008h PCOR 0009h to 000Bh 000Ch LTCSR2 000Dh LTARR LITE 000Eh LTCNTR ...

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... DMBK2L 0050h DMCR2 Clock 0051h CKCNTCSR Controller 0052h to 0054h 22/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 (1) (continued) Register name Interrupt Software Priority register 0 Interrupt Software Priority register 1 Interrupt Software Priority register 2 Interrupt Software Priority register 3 External Interrupt Control register Reserved area (1 byte) Watchdog Control register ...

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... SPI SPICR 0072h SPISR 1. Legend: x=undefined, R/W=read/write. 2. Reset status is 03h for ST7FOXK2 and 00h for ST7FOXF1 and ST7FOXK1 3. For a description of the Debug Module registers, see ICC protocol reference manual. 4. Available on ST7FOXK2 only (1) (continued) Register name Timer A Control register 2 Timer A Control register 1 ...

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... ST7 enters ICC mode, it fetches a specific Reset vector which points to the ST7 System Memory containing the ICC protocol routine. This routine enables the ST7 to receive bytes from the ICC interface. Download ICP Driver code in RAM from the ICCDATA pin Execute ICP Driver code in RAM to program the Flash memory 24/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Depending on the ICP Driver code downloaded in RAM, Flash memory programming can be fully customized (number of bytes to program, program locations, or selection of the serial communication interface for downloading). 4.3.2 In Application Programming (IAP) This mode uses an IAP Driver program previously programmed in Sector 0 by the user (in ICP mode) ...

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... In the application, even if the pin is configured as output, any reset will put it back in input pull-up. Figure 6. Typical ICC Interface (See Note 3) APPLICATION POWER SUPPLY 26/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 PROGRAMMING TOOL ICC CONNECTOR ICC Cable ICC CONNECTOR HE10 CONNECTOR TYPE OPTIONAL (See Note 4) ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 4.5 Memory protection There are two different types of memory protection: Read-Out Protection and Write/Erase Protection which can be applied individually. 4.5.1 Read-out protection Read-Out Protection, when selected provides a protection against program memory content extraction and against write access to Flash memory. Even if no protection can be considered as totally unbreakable, the feature provides a very high level of protection for a general purpose microcontroller ...

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... When an EPB or another programming tool is used (in socket or ICP mode), the RASS keys are sent automatically. Reset value: 000 0000 (00h Table 5. Flash register mapping and reset values Address Register 7 label (Hex.) FCSR - 0034 0 Reset Value 28/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Read/write OPT LAT ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 5 Central processing unit 5.1 Introduction This CPU has a full 8-bit architecture and contains six internal registers allowing efficient 8- bit data manipulation. 5.2 Main features 63 basic instructions Fast 8-bit by 8-bit multiply 17 main addressing modes Two 8-bit index registers 16-bit stack pointer ...

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... This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction reset by hardware during the same instructions half carry has occurred half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. 30/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Read/write 0 N ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit Interrupt mask bit This bit is set by hardware when entering in interrupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET instructions and is tested by the JRM and JRNM instructions ...

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... A subroutine call occupies two locations and an interrupt five locations in the stack area. 32/226 Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable Read/write Figure ST7FOXF1, ST7FOXK1, ST7FOXK2 SP6 SP5 SP4 SP3 SP2 SP1 SP0 8 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 8. Stack manipulation example CALL Subroutine @ 0180h SP SP PCH @ 01FFh PCL Stack Higher Address = 01FFh Stack Lower Address = 0180h PUSH Y POP Y Interrupt Event PCH PCH PCH PCL PCL PCL PCH PCH PCH PCL ...

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... Section 12: Electrical characteristics on page 187 and accuracy of the RC oscillator. To improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100 nF, between the V V pins as close as possible to the ST7 device. SSA 34/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 supply voltage at 25 °C (see DD Conditions 25° ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 These bytes are systematically programmed by ST. 6.1.2 Customized RC calibration If the application requires a higher frequency accuracy or if the voltage or temperature conditions change in the application, the frequency may need to be recalibrated. Two non- volatile bytes (RCCRH_USER and RCCRL_USER) are reserved for storing these new values ...

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... Wait 3 AWU RC cycles till the AWU_FLAG is set 4. The switch to the AWU clock is made at the positive edge of the AWU clock signal 5. Once the switch is made, the internal RC is stopped 36/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 READ OPERATION NOT POSSIBLE ERASE CYCLE WRITE CYCLE t PROG Section 13 ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Case 2 Switching from AWU RC to internal RC 1. Reset the RC/AWU bit to enable the internal RC oscillator 2. Using a 4-bit counter, wait until 8 internal RC cycles have elapsed. The counter is running on internal RC clock. 3. Wait till the AWU_FLAG is cleared (1AWU RC cycle) and the RC_FLAG is set (2 RC cycles) 4 ...

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... Clock controller RC OSC /2 CLKIN/2 DIVIDER OSC /2 DIVIDER 8-BIT LITE TIMER 2 COUNTER f /32 OSC OSC MCCSR MCO SMS ST7FOXF1, ST7FOXK1, ST7FOXK2 RCCRH RCCRL CKCNTCSR RC/AWU 12-BIT f CPU AT TIMER 2 AWU RC OSC f OSC CLKIN/2 OSC/2 CLKSEL[1:0] Option bits f LTIMER (1ms timebase @ 8 MHz f ) OSC ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 6.2.1 External clock source In this external clock mode, a clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC1 pin while the OSC2 pin is tied to ground. Note: When the Multi-Oscillator is not used OSCI1 and OSCI2 must be tied to ground, and PB1 is selected by default as the external clock ...

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... Reset state. The shorter or longer clock cycle delay is automatically selected depending on the clock source chosen by option byte. The Reset vector fetch phase duration is 2 clock cycles. 40/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Hardware configuration ST7 OSC1 OSC2 ...

Page 41

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 9. CPU clock delay during Reset sequence External clock (connected to CLKIN/PB1 pin) External Crystal/Ceramic Oscillator (connected to OSC1/OSC2 pins) External Crystal/Ceramic 1-16 MHz Oscillator External Crystal/Ceramic 32 kHz Oscillator Figure 13. Reset sequence phases Clock source Internal RC 8 MHz Oscillator Internal RC 32 kHz Oscillator ...

Page 42

... OSC supply can generally be provided by an external DD lower than V (falling edge) as shown in DD IT- larger than t DD g(VDD) ST7FOXF1, ST7FOXK1, ST7FOXK2 weak pull-up ON sequences). This detection is INTERNAL RESET ___ WATCHDOG RESET ___ ILLEGAL OPCODE RESET ___ LVD RESET frequency ...

Page 43

... ST7FOXF1, ST7FOXK1, ST7FOXK2 6.3.5 Internal watchdog reset The Reset sequence generated by an internal watchdog counter overflow is shown in Figure 15: Reset sequences Starting from the watchdog counter underflow, the device RESET pin acts as an output that is pulled low during at least t Figure 15. Reset sequences V DD ...

Page 44

... DD is falling DD Figure 16. value (guaranteed for the oscillator frequency) is above V DD down ensure optimum restart DD Figure 89 on page 207 supply voltage rises monotonously when the DD ST7FOXF1, ST7FOXK1, ST7FOXK2 DD reference value IT+(LVD) is below: DD Section 13.1 on page and note 4. Section 13.1 on supply , IT-(LVD) ...

Page 45

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 16. Low voltage detector vs reset IT+(LVD) V IT-(LVD) RESET Figure 17. Reset and supply management block diagram RESET SEQUENCE RESET hys WATCHDOG TIMER (WDG) SYSTEM INTEGRITY MANAGEMENT MANAGER RCCRL (RSM) 0 CR1 CR0 Supply, reset and clock management ...

Page 46

... This bit is read/write by software and cleared by hardware after a reset. This bit selects the input clock f 0: Normal mode (f 1: Slow mode (f 46/226 0 0 Read/write 0 0 Read/write or f /32. OSC OSC f CPU = OSC f /32) CPU = OSC ST7FOXF1, ST7FOXK1, ST7FOXK2 0 0 RCCLAT 0 0 MCO 0 RCCPGM 0 SMS ...

Page 47

... ST7FOXF1, ST7FOXK1, ST7FOXK2 6.5.3 RC Control Register High (RCCRH) Reset value: 1111 1111 (FFh) 7 CR9 CR8 Bits 7:0 = CR[9:2] RC Oscillator Frequency Adjustment bits These bits must be written immediately after reset to adjust the RC oscillator frequency. The application can store the correct value for each voltage range in Flash memory and write it to this register at start-up ...

Page 48

... In this case, a watchdog reset can be detected by software while an external reset can not. Bits 1:0 = Reserved, must be kept cleared 48/226 CR0 WDGRF 0 Read/write 34. RESET source External RESET pin Watchdog LVD ST7FOXF1, ST7FOXK1, ST7FOXK2 LVDRF 0 Section 6.1.1: Internal RC Table 10: Reset source selection on LVDRF WDGRF ...

Page 49

... Bits 4:2 = Reserved, must be cleared. Bits 1:0 = Must be set. Caution: For ST7FOXF1 and ST7FOXK1 devices, PRSC[1:0] bits must be forced software in order to reduce current consumption. 6.5.6 Clock controller control/status register (CKCNTCSR) Reset value: 0000 1001 (09h Bits 7:4 = Reserved, must be kept cleared. ...

Page 50

... CR8 CR7 CR6 CR1 CR0 WDGRF CK1 CK0 - AWU_ - - - FLAG ST7FOXF1, ST7FOXK1, ST7FOXK2 RCCLAT RCCPGM MCO CR5 CR4 CR3 LVDRF - RC_FLA - RC/AWU ...

Page 51

... ST7FOXF1, ST7FOXK1, ST7FOXK2 7 Interrupts 7.1 Introduction The ST7 enhanced interrupt management provides the following features: Hardware interrupts Software interrupt (TRAP) Nested or concurrent interrupt management with flexible interrupt priority and level management: – software programmable nesting levels – 13 interrupt vectors fixed by hardware – ...

Page 52

... Interrupt software priority levels Interrupt software priority Level 0 (main) Level 1 Level 2 Level 3 (= interrupt disable) Figure 18. Interrupt processing flowchart RESET RESTORE PC FROM STACK 52/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Level Low High PENDING Y INTERRUPT Interrupt has the same lower software priority than current one ...

Page 53

... ST7FOXF1, ST7FOXK1, ST7FOXK2 7.2.1 Servicing pending interrupts As several interrupts can be pending at the same time, the interrupt to be taken into account is determined by the following two-step process: The highest software priority interrupt is serviced, If several interrupts have the same software priority then the interrupt with the highest hardware priority is serviced first ...

Page 54

... Note interrupt, that is not able to Exit from Halt mode, is pending with the highest priority when exiting Halt mode, this interrupt is serviced after the first one serviced. 54/226 Table 17: ST7FOXF1/ST7FOXK1 Interrupt Table 17: ST7FOXF1/ST7FOXK1 Interrupt Figure 19. ST7FOXF1, ST7FOXK1, ST7FOXK2 mapping ...

Page 55

... ST7FOXF1, ST7FOXK1, ST7FOXK2 7.4 Concurrent and nested management The following Figure 20 first is called concurrent mode and does not allow an interrupt to be interrupted, unlike the nested mode in Figure lowest to the highest: MAIN, IT5, IT4, IT3, IT2, IT1, IT0. The software priority is given for each interrupt ...

Page 56

... Read/write Table 16: Dedicated interrupt instruction Level 0 (main) Level 1 Level 2 7 I1_3 I0_3 I1_2 I0_2 I1_7 I0_7 I1_6 I0_6 I1_11 I0_11 I1_10 I0_10 ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 14). set). Level I1 1 Low 0 High 1 I1_1 I0_1 I1_0 I1_5 I0_5 I1_4 I1_9 I0_9 ...

Page 57

... ST7FOXF1, ST7FOXK1, ST7FOXK2 The RESET and TRAP vectors have no software priorities. When one is serviced, the I1 and I0 bits of the CC register are both set. Level 0 cannot be written (I1_x = 1, I0_x = 0). In this case, the previously stored value is kept (Example: previous = CFh, write = 64h, result = 44h). ...

Page 58

... This interrupt exits the MCU from Auto Wake-up from Halt mode only. 3. These interrupts exit the MCU from Active-Halt mode only. 58/226 Description Reset Software interrupt Auto Wake Up interrupt AWUCSR Reserved interrupt Lite timer RTC interrupt ST7FOXF1, ST7FOXK1, ST7FOXK2 Exit from Register Priority HALT label order or AWUFH (1) yes FFFEh-FFFFh ...

Page 59

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 18. ST7FOXK2 interrupt mapping Source Number block RESET TRAP 0 AWU ei0 External interrupt 0 (Port A) 5 ei1 External interrupt 1 (Port B) 6 ei2 External interrupt 2 (Port C) AT timer input Capture/Output 7 AT TIMER ( timer overflow 1 interrupt 9 AT timer Overflow 2 interrupt ...

Page 60

... Table 19. Interrupt sensitivity bits ISx1 ISx0 60/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 IS21 IS20 IS11 Read/write External interrupt sensitivity Falling edge & low level Rising edge only Falling edge only Rising and falling edge 0 IS10 IS01 IS00 Table 19 ...

Page 61

... ST7FOXF1, ST7FOXK1, ST7FOXK2 8 Power saving modes 8.1 Introduction To give a large measure of flexibility to the application in terms of power consumption, four main power saving modes are implemented in the ST7 (see Slow Wait (and Slow-Wait) Active Halt Auto wakeup From Halt (AWUFH) Halt After a reset the normal operating mode is selected by default (Run mode). This mode ...

Page 62

... The MCU will remain in Wait mode until a Reset or an Interrupt occurs, causing it to wake up. Refer to Figure 24 62/226 ) to the available supply voltage. CPU f OSC f CPU f OSC SMS for a description of the Wait mode flowchart. ST7FOXF1, ST7FOXK1, ST7FOXK2 /32 f OSC NORMAL RUN MODE REQUEST ...

Page 63

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 24. Wait mode flowchart 1. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. 8.4 Active-halt and halt modes Active-Halt and Halt modes are the two lowest power consumption modes of the MCU. They are both entered by executing the ‘ ...

Page 64

... Figure 25. Active-halt timing overview [Active Halt Enabled] 1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET. 64/226 Figure 26). ACTIVE 256 CPU RUN HALT 1) CYCLE DELAY RESET OR HALT INTERRUPT FETCH INSTRUCTION VECTOR ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure RUN 26). ...

Page 65

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 26. Active-halt mode flowchart 1. This delay occurs only if the MCU exits Active-Halt mode by means of a RESET. 2. Peripherals clocked with an external clock source can still be active. 3. Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode. ...

Page 66

... Peripheral clocked with an external clock source can still be active. 3. Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to Table 17: ST7FOXF1/ST7FOXK1 Interrupt 4. Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set during the interrupt routine and cleared when the CC register is popped. ...

Page 67

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Halt mode recommendations Make sure that an external event is available to wake up the microcontroller from Halt mode. When using an external interrupt to wake up the microcontroller, reinitialize the corresponding I/O as “Input Pull-up with Interrupt” before executing the HALT instruction. The main reason for this is that the I/O may be wrongly configured due to external interference unforeseen logical condition ...

Page 68

... AWUFH interrupt 68/226 and then calculating the right prescaler value. AWU_RC to the Input Capture of the 8-bit Lite timer, allowing the AWU_RC Section 8.4: Active-halt and halt t AWU HALT MODE ST7FOXF1, ST7FOXK1, ST7FOXK2 ). Its frequency is divided by AWU_RC modes). 256 t RUN MODE CPU Clear by software ...

Page 69

... N 3) INTERRUPT AWU RC OSC Y MAIN OSC PERIPHERALS CPU I[1:0] BITS 256 CPU CLOCK CYCLE AWU RC OSC MAIN OSC PERIPHERALS CPU I[1:0] BITS FETCH RESET VECTOR OR SERVICE INTERRUPT Table 17: ST7FOXF1/ST7FOXK1 Interrupt mapping Power saving modes WATCHDOG DISABLE ON OFF 2) OFF OFF 10 RESET Y OFF ON OFF ...

Page 70

... AWUFH (Auto wakeup from Halt) mode disabled 1: AWUFH (Auto wakeup from Halt) mode enabled Note: Whatever the clock source, this bit should be set to enable the AWUFH mode once the HALT instruction has been executed. 70/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Read/Write 0 AWU ...

Page 71

... ST7FOXF1, ST7FOXK1, ST7FOXK2 8.5.3 AWUFH prescaler register (AWUPR) Reset value: 1111 1111 (FFh) 7 AWUPR7 AWUPR6 Bits 7:0= AWUPR[7:0] Auto wakeup Prescaler These 8 bits define the AWUPR Dividing factor (see Table 21. Configuring the dividing factor AWUPR[7:0 00h 01h ... FEh FFh In AWU mode, the time during which the MCU stays in Halt mode, t equation below ...

Page 72

... External interrupts are hardware interrupts. Fetching the corresponding interrupt vector automatically clears the request latch. Changing the sensitivity of a particular external interrupt clears this pending interrupt. This can be used to clear unwanted pending interrupts. 72/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

Page 73

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Spurious interrupts When enabling/disabling an external interrupt by setting/resetting the related OR register bit, a spurious interrupt is generated if the pin level is low and its edge sensitivity includes falling/rising edge. This is due to the edge detector input which is switched to '1' when the external interrupt is disabled by the OR register. ...

Page 74

... ALTERNATE ENABLE BIT If implemented 1 0 Combinational Logic FROM OTHER BITS Note: Refer to the Port Configuration table for device specific information. ST7FOXF1, ST7FOXK1, ST7FOXK2 and Table 3 describe which peripheral P-BUFFER V DD (see table below) PULL-UP (see table below PULL-UP PAD CONDITION ...

Page 75

... Pull-up with Interrupt Output Open Drain (logic level) 1. Off means implemented not activated, On means implemented and activated. Table 25. ST7FOXF1/ST7FOXK1/ST7FOXK2 I/O port configuration PAD PAD PAD 1. When the I/O port is in input configuration and the associated alternate function is enabled as an output, reading the DR register will read the alternate function output status. ...

Page 76

... INPUT OUTPUT floating/pull-up floating open-drain interrupt (reset state) XX Description No effect on I/O ports. External interrupts cause the device to exit from Wait No effect on I/O ports. External interrupts cause the device to exit from Halt ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 11 OUTPUT push-pull = DDR, OR Section 12.9: I/O port mode. mode. 33. ...

Page 77

... ST7FOXF1, ST7FOXK1, ST7FOXK2 9.6 Interrupts The external interrupt event generates an interrupt if the corresponding configuration is selected with DDR and OR registers and if the I bit in the CC register is cleared (RIM instruction). Table 27. Description of interrupt events Interrupt Event External interrupt on selected external event See application notes AN1045 software implementation of software LCD driver 9 ...

Page 78

... ST7FOXF1, ST7FOXK1, ST7FOXK2 DDR Output open drain true open drain open drain open drain pull-up open drain ...

Page 79

... ST7FOXF1, ST7FOXK1, ST7FOXK2 10 On-chip peripherals 10.1 Watchdog timer (WDG) 10.1.1 Introduction The Watchdog timer is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The Watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the counter’ ...

Page 80

... If Halt mode with Watchdog is enabled by option byte (No watchdog reset on HALT instruction recommended before executing the HALT instruction to refresh the WDG counter, to avoid an unexpected WDG reset immediately after waking up the microcontroller. Same behavior in active-halt mode. 10.1.5 Interrupts None. 80/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 timing): (1)( MHz CPU min [ms] ...

Page 81

... ST7FOXF1, ST7FOXK1, ST7FOXK2 10.1.6 Register description Control register (WDGCR) Reset value: 0111 1111 (7Fh) 7 WDGA Bit 7 = WDGA Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watchdog option is enabled by option byte. ...

Page 82

... Output Compare mode Input Capture mode – 12-bit Input Capture register (ATICR) – Triggered by rising and falling edges – Maskable IC interrupt – Long range Input Capture Internal/External Break control Flexible Clock control One Pulse mode on PWM2/3 Force update 82/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ) CPU ...

Page 83

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 35. Single timer mode (ENCNTR2=0) ATIC Edge Detection Circuit 12-Bit Autoreload register 1 Clock Control Figure 36. Dual timer mode (ENCNTR2=1) Edge Detection Circuit ATIC 12-Bit Autoreload register 1 12-Bit Autoreload register 2 Control LTIC 12-bit Input Capture PWM0 Duty Cycle Generator ...

Page 84

... See 84/226 Figure 35 and Figure 36). The frequency is controlled by the counter ⁄ 4096 ATR PWM COUNTER equals 4 MHz COUNTER ⁄ Resolution 1 4096 ATR Figure 37. ST7FOXF1, ST7FOXK1, ST7FOXK2 ) or can have two different PWM ) – the maximum value – is PWM ...

Page 85

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 37. PWM polarity inversion The Data Flip Flop (DFF) applies the polarity inversion when triggered by the counter overflow input. Output control The PWMx output signals can be enabled or disabled using the OEx bits in the PWMCR register. Figure 38. PWM function ...

Page 86

... OP0 and OP1 are not set. If polarity is inverted, overlapping PWM0/PWM1 signals will be generated. 3 Dead Time generation does not work at 1msec timebase. 86/226 ATR= FFDh FFDh FFEh FFFh FFDh [ ] Tcounter1 × = Dead time DT 6:0 ST7FOXF1, ST7FOXK1, ST7FOXK2 FFEh FFFh FFDh FFEh ≠ DTE is set and DT[6:0]=0, t ...

Page 87

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 40. Dead time generation CK_CNTR1 CNTR1 PWM 0 PWM 1 PWM 0 PWM 1 In the above example, when the DTE bit is set: PWM goes low at DCR0 match and goes high at ATR1+Tdt PWM1 goes high at DCR0+Tdt and goes low at ATR match. With this programmable delay (Tdt), the PWM0 and PWM1 signals which are generated are not overlapped ...

Page 88

... When the break function is deactivated after applying the break (BA bit goes from software), Timer takes the control of PWM ports. Note: The break function of the ST7FOXK2 is different from the break function of the ST7FOXF1/ST7FOXK1. Refer to function on page 88 Figure 41. ST7FOXF1/ST7FOXK1 Block diagram of break function BREAK pin BREAKEN register BREN2 88/226 Figure 41: ST7FOXF1/ST7FOXK1 Block diagram of break ...

Page 89

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 42. ST7FOXK2 Block diagram of break function BREAK1 pin Comparator1 BREAKCR2 register BR2SEL BR2EDGE BREAK2 pin Comparator2 Output compare mode To use this function, load a 12-bit value in the Preload DCRxH and DCRxL registers. When the 12-bit upcounter CNTR1 reaches the value stored in the Active DCRxH and DCRxL registers, the CMPFx bit in the PWMxCSR register is set and an interrupt request is generated if the CMPIE bit is set ...

Page 90

... CPU OFF 90/226 ACTIVE DUTY CYCLE REGx OUTPUT COMPARE CIRCUIT COUNTER 1 CMP INTERRUPT REQUEST 12-BIT INPUT CAPTURE REGISTER ATICR IC INTERRUPT REQUEST ICF ICIE CK1 CK0 12-BIT UPCOUNTER1 CNTR1 12-BIT AUTORELOAD REGISTER ATR1 ST7FOXF1, ST7FOXK1, ST7FOXK2 CMPFx (PWMxCSR) CMPIE (ATCSR) ...

Page 91

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 45. Input capture timing diagram f COUNTER COUNTER1 01h ATIC PIN ICF FLAG Long range input capture Pulses that last more than 8 µs can be measured with an accuracy of 4 µ MHz in the following conditions: The 12-bit AT4 timer is clocked by the Lite timer (RTC pulse: CK[1: the ATCSR ...

Page 92

... Now pulse width P between first capture and second capture is given by where N is the number of overflows of 12-bit CNTR1. 92/226 × – + decimal F9 LT1 LT2 ( ( × decimal FFF N N ATICR2 ATICR1 ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 47 on page 93. ) × 0.004ms ) × – – 1 1ms ...

Page 93

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 47. Long range input capture timing diagram f OSC/32 TB Counter1 F9h CNTR1 LTIC LTICR ATICRH ATICRL 00h LT1 F9h 00h ATH1 & ATL1 00h LT1 0h ATH1 00h ATL1 On-chip peripherals LT2 ATH2 & ...

Page 94

... ATR2 value should be changed after an overflow in one pulse mode to avoid any irregular PWM cycle. When exiting from one pulse mode, the OP_EN bit in the PWM3CSR register should be reset first and then the ENCNTR2 bit (if counter 2 must be stopped). 94/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ). CPU CPU ...

Page 95

... ST7FOXF1, ST7FOXK1, ST7FOXK2 How to enter one pulse mode The steps required to enter One Pulse mode are the following: 1. Load ATR2H/ATR2L with required value. 2. Load DCR3H/DCR3L for PWM3. ATR2 value must be greater than DCR3. 3. Set OP3 in PWM3CSR if polarity change is required. 4. Select CNTR2 by setting ENCNTR2 bit in ATCSR2. ...

Page 96

... On-chip peripherals Figure 50. Dynamic DCR2/3 update in one pulse mode f counter2 CNTR2 LTIC FORCE2 TRAN2 DCR2/3 PWM2/3 96/226 (DCR3) 000 FFF 000 old (DCR2/3) old extra PWM3 period due to DCR3 update dynamically in one-pulse mode. ST7FOXF1, ST7FOXK1, ST7FOXK2 (DCR3) ATR2 000 new (DCR2/3) new ...

Page 97

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Force update In order not to wait for the counter programmable counter which when set, make the counters start with the overflow value, i.e. FFFh. After overflow, the counters start counting from their respective auto reload register values. These bits are FORCE1 and FORCE2 in the ATCSR2 register. FORCE1 is used to force an overflow on Counter 1 and, FORCE2 is used for Counter 2 ...

Page 98

... This bit is read/write by software and cleared by hardware after a reset. 0: Overflow Interrupt Disabled. 1: Overflow Interrupt Enabled. 98/226 ICIE CK1 Read / Write Counter clock selection OFF selection forbidden timebase @ 8 MHz) LTIMER f CPU ST7FOXF1, ST7FOXK1, ST7FOXK2 CK0 OVF1 OVFIE1 CK1 CMPIE CK0 ...

Page 99

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 0 = CMPIE Compare Interrupt Enable bit This bit is read/write by software and cleared by hardware after a reset. it can be used to mask the interrupt generated when any of the cmpfx bit is set. 0: Output Compare Interrupt Disabled. 1: Output Compare Interrupt Enabled. Counter register 1 High (CNTR1H) ...

Page 100

... PWM mode disabled. PWMx Output Alternate function disabled (I/O pin free for general purpose I/O) 1: PWM mode enabled PWMX control status register (PWMxCSR) Reset value: 0000 0000 (00h Bits 7:4= Reserved, must be kept cleared. Bit 3 = OP_EN One Pulse Mode Enable bit 100/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 0 0 ATR11 Read/write ATR5 ATR4 ATR3 Read/write 0 OE2 ...

Page 101

... Break 1 signal from external BREAK1 pin and the output of the comparator. 0: External BREAK1 pin is selected for break mode. 1: Comparator 1 output is selected for break mode. Bit 6 = BR1EDGE Break 1 input edge selection bit (BREDGE on ST7FOXF1/ST7FOXK1) This bit is read/write by software and cleared by hardware after reset. It selects the active level of Break 1 signal. ...

Page 102

... On-chip peripherals Bit 5 = BA1 Break 1 Active bit (BA on ST7FOXF1/ST7FOXK1) This bit is read/write by software, cleared by hardware after reset and set by hardware when the active level defined by the BR1EDGE bit is applied on the BREAK1 pin. It activates/deactivates the Break 1function. 0: Break 1not active 1: Break 1active Bit 4 = BP1EN Break 1Pin Enable bit (BPEN on ST7FOXF1/ST7FOXK1) This bit is read/write by software and cleared by hardware after Reset ...

Page 103

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Break control register 2 (BREAKCR2) Reset value: 0000 0000 (00h) 7 BR2SEL BR2EDGE Note: This register is available on ST7FOXK2 only Bit 7 = BR2SEL Break 2 input selection bit This bit is read/write by software and cleared by hardware after reset. It selects the active Break 2 signal from external BREAK2 pin and the output of the comparator. ...

Page 104

... Reset value: 0000 0000 (00h Bits 15:12 = Reserved. 104/226 0 0 Read/write DCR5 DCR4 Read/write Figure 38). In Output Compare mode, they define the value Read only ST7FOXF1, ST7FOXK1, ST7FOXK2 DCR11 DCR10 DCR9 DCR3 DCR2 DCR1 Figure 38). ICR11 ICR10 ICR9 8 DCR8 0 DCR0 8 ...

Page 105

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Input Capture register Low (ATICRL) Reset value: 0000 0000 (00h) 7 ICR7 ICR6 Bits 11:0 = ICR[11:0] Input Capture Data. This is a 12-bit register which is readable by software and cleared by hardware after a reset. The ATICR register contains captured the value of the 12-bit CNTR1 register when a rising or falling edge occurs on the ATIC or LTIC pin (depending on ICS) ...

Page 106

... If this bit is set, PWM2/3 will be generated using CNTR2. 0: PWM2/3 is generated using CNTR1. 1: PWM2/3 is generated using CNTR2. Note: Counter 2 gets frozen when the ENCNTR2 bit is reset. When ENCNTR2 is set again, the counter will restart from the last value. 106/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ICS OVFIE2 OVF2 Read/write 0 ENCNTR2 ...

Page 107

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 1= TRAN2 Transfer enable2 bit This bit is read/write by software, cleared by hardware after each completed transfer and set by hardware after reset. It controls the transfers on CNTR2. It allows the value of the Preload DCRx registers to be transferred to the Active DCRx registers after the next overflow event. ...

Page 108

... ATR6 ATR5 ATR4 OE3 OE2 ST7FOXF1, ST7FOXK1, ST7FOXK2 DT3 DT2 DT1 CK0 OVF1 OVFIE1 CNTR1_1 CNTR1_1 CNTR1_9 CNTR1_3 CNTR1_2 CNTR1_1 ATR11 ATR10 ATR9 0 0 ...

Page 109

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 38. Register mapping and reset values (continued) Add. Register 7 (Hex) label DCR0L DCR7 001C Reset Value 0 DCR1H 001D 0 Reset Value DCR1L DCR7 001E Reset Value 0 DCR2H 001F 0 Reset Value DCR2L DCR7 0020 Reset Value 0 DCR3H 0021 0 Reset Value ...

Page 110

... Enabled by hardware or software (configurable by option byte) – Optional reset on HALT instruction (configurable by option byte) – Automatically resets the device unless disable bit is refreshed – Software reset (Forced Watchdog reset) – Watchdog reset status flag 110/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 ) OSC ) OSC ...

Page 111

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 52. Lite timer 2 block diagram f /32 OSC LTCNTR 8-bit TIMEBASE COUNTER 2 LTARR 8-bit AUTORELOAD REGISTER 8-bit TIMEBASE COUNTER 1 LTICR LTIC INPUT CAPTURE REGISTER 10.3.3 Functional description Timebase Counter 1 The 8-bit value of Counter 1 cannot be read or written by software. After an MCU reset, it starts incrementing from frequency of f counter rolls over from F9h to 00h ...

Page 112

... MHz f ) OSC 01h 02h 03h 04h xxh . This means that software must write to the WDGD bit at WDG ST7FOXF1, ST7FOXK1, ST7FOXK2 /32 starting from the value OSC CLEARED BY S/W READING 05h 06h 07h LTIC REGISTER 07h 04h Figure 54 ...

Page 113

... ST7FOXF1, ST7FOXK1, ST7FOXK2 In this case, the HALT instruction stops the oscillator. When the oscillator is stopped, the Lite timer stops counting and is no longer able to generate a Watchdog reset until the microcontroller receives an external interrupt or a reset external interrupt is received, the WDG restarts counting after 4096 CPU clocks reset is generated, the Watchdog is disabled (reset state) ...

Page 114

... Timebase (TB2) interrupt enabled Bit 0 = TB2F Timebase 2 Interrupt flag This bit is set by hardware and cleared by software reading the LTCSR register. Writing to this bit has no effect Counter 2 overflow 1: A Counter 2 overflow has occurred 114/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Enable Exit Event Control from Flag ...

Page 115

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Lite Timer Autoreload register (LTARR) Reset value: 0000 0000 (00h) 7 AR7 AR6 Bits 7:0 = AR[7:0] Counter 2 Reload value These bits register is read/write by software. The LTARR value is automatically loaded into Counter 2 (LTCNTR) when an overflow occurs. Lite Timer Counter 2 (LTCNTR) Reset value: 0000 0000 (00h) ...

Page 116

... Read only AR6 AR5 AR4 CNT6 CNT5 CNT4 ICF TB TB1IE ICR6 ICR5 ICR4 ST7FOXF1, ST7FOXK1, ST7FOXK2 ICR2 ICR1 ICR0 TB2IE AR3 AR2 AR1 CNT3 CNT2 CNT1 TB1F ICR3 ICR2 ICR1 0 ...

Page 117

... ST7FOXF1, ST7FOXK1, ST7FOXK2 10.4 16-bit timer 10.4.1 Introduction The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including pulse length measurement two input signals (input capture) or generation two output waveforms (output compare and PWM). ...

Page 118

... The value in the counter register repeats every 131 072, 262 144 or 524 288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can external frequency. CPU 118/226 (see16-bit read sequence (from either the counter register or the 120). ST7FOXF1, ST7FOXK1, ST7FOXK2 /2, f CPU CPU /4, ...

Page 119

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 55. Timer block diagram f CPU 8 high EXEDG 1/2 1/4 1/8 EXTCLK pin CC[1:0] Overflow detect circuit ICF1 OCF1 TOF ICF2 CSR (control/status register ICIE OCIE TOIE FOLV2 (1) Timer interrupt 1. If IC, OC and TO interrupt requests have separate vectors ST7FOXF1/ST7FOXK1 Interrupt mapping) Internal bus ...

Page 120

... EXTCLK that triggers the free running counter. The counter is synchronized with the falling edge of the internal CPU clock. 120/226 Beginning of the sequence Read MSB At t0 Other instructions Returns the buffered Read LSB At t0 +∆t Sequence completed ST7FOXF1, ST7FOXK1, ST7FOXK2 LSB is buffered LSB value at t0 ...

Page 121

... ST7FOXF1, ST7FOXK1, ST7FOXK2 A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock frequency must be less than a quarter of the CPU clock frequency. Figure 57. Counter timing diagram, internal clock divided by 2 Timer overflow flag (TOF) Figure 58 ...

Page 122

... The alternate inputs (ICAP1 and ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input capture function. Moreover if one of the ICAPi pin is configured as an input and the second one as an output, an interrupt can be generated if 122/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 MSB ICiHR Figure 61) ...

Page 123

... ST7FOXF1, ST7FOXK1, ST7FOXK2 the user toggle the output pin and if the ICIE bit is set. This can be avoided if the input capture function i is disabled by reading the ICiHR (see note 1). 6 The TOF bit can be used with interrupt in order to measure event that go beyond the timer range (FFFFh) ...

Page 124

... Set the OCFi bit. The OCMPi pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). A timer interrupt is generated if the OCIE bit is set in the CR2 register and the I bit is cleared in the CC register (CC). 124/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 MSB OCiHR R value to 8000h. i ...

Page 125

... ST7FOXF1, ST7FOXK1, ST7FOXK2 The OC R register value required for a specific timing application can be calculated using i the following formula: Equation 1 Where: ∆ output compare period (in seconds CPU clock frequency (in hertz) CPU = timer prescaler factor ( depending on CC[1:0] bits, see PRESC Control register 2 (TACR2) on page ...

Page 126

... OC1E CC1 OC2E CR2 (control register 2) CR1 (control register 1) FOLV2 FOLV1 OCIE OLVL2 OCF1 OCF2 = f TIMER CPU Timer clock 2ECF 2ED0 2ED1 Counter register ST7FOXF1, ST7FOXK1, ST7FOXK2 CC0 OLVL1 Latch 1 Latch (status register) /2 2ED2 2ED4 2ED3 2ED3 OCMP1 pin ...

Page 127

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 64. Output compare timing diagram, f Output compare register i (OCRi) Output compare flag i (OCFi) One pulse mode One pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. ...

Page 128

... OLVL1 bit is output on the OCMP1 pin, (see 128/226 One pulse mode cycle When event occurs on ICAP1 When counter = OC1R t OCiR value = PRESC EXT Figure ST7FOXF1, ST7FOXK1, ST7FOXK2 ICR1 = counter OCMP1 = OLVL2 to FFFCh Counter is reset ICF1 bit is set OCMP1 = OLVL1 CPU 134) 66). : Timer A ...

Page 129

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Note: 1 The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate an output compare interrupt. 2 When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the PWM mode is the only active one. ...

Page 130

... Figure 68. Pulse width modulation cycle If OLVL = 1 and OLVL2 = 0 the length of the positive pulse is the difference between the OC2R and OC1R registers. If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin. 130/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Equation 5. (see: Timer A Control register 2 (TACR2) on page Pulse width modulation cycle ...

Page 131

... ST7FOXF1, ST7FOXK1, ST7FOXK2 The OC R register value required for a specific timing application can be calculated using i the following formula: Equation 5 Where signal or pulse period (in seconds CPU clock frequency (in hertz) CPU = timer prescaler factor ( depending on CC[1:0] bits, see PRESC register 2 (TACR2) on page ...

Page 132

... Pulse width modulation mode on page 132/226 Interrupt event Input capture 1 (2) Yes (2) and/or Yes No Not recommended No Not recommended 127. 127. 129. ST7FOXF1, ST7FOXK1, ST7FOXK2 (1) Event Enable Exit from flag control bit WAIT ICF1 Yes ICIE ICF2 Yes OCF1 Yes OCIE OCF2 ...

Page 133

... ST7FOXF1, ST7FOXK1, ST7FOXK2 10.4.7 16-bit timer registers Each timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the alternate counter. TIMA Control register 1 (TACR1) ...

Page 134

... OC1R register; the period depends on the value of OC2R register. Bits 3:2 CC[1:0] Clock control The timer clock mode depends on the following bits: 00: Timer clock = f 01: Timer clock = f 134/226 OPM PWM Read / Write /4 CPU /2 CPU ST7FOXF1, ST7FOXK1, ST7FOXK2 CC[1:0] IEDG2 EXEDG 0 ...

Page 135

... ST7FOXF1, ST7FOXK1, ST7FOXK2 10: Timer clock = f 11: Timer clock = external clock (where available) Note: If the external clock pin is not available, programming the external clock configuration stops the counter. Bit 1 = IEDG2 Input edge 2 This bit determines which type of level transition on the ICAP2 pin triggers the capture. ...

Page 136

... MSB Timer A Input capture 1 low register (TAIC1LR) Reset value: undefined This is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 1 event). 7 MSB 136/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Read Only Read Only 0 LSB 0 LSB ...

Page 137

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Timer A Output compare 1 high register (TAOC1HR) Reset value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. 7 MSB Timer A Output compare 1 low register (TAOC1LR) Reset value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register ...

Page 138

... This is an 8-bit read-only register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to CSR register does not clear the TOF bit in the CSR register. 7 MSB 138/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Read Only Read Only Read Only Read Only 0 ...

Page 139

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Input capture 2 high register (IC2HR) Reset value: undefined This is an 8-bit read-only register that contains the high part of the counter value (transferred by the input capture 2 event). 7 MSB Input capture 2 low register (IC2LR) Reset value: undefined This is an 8-bit read-only register that contains the low part of the counter value (transferred by the input capture 2 event) ...

Page 140

... Address (Hex.) Register label TAACHR 5E Reset value TAACLR 5F Reset value TAICHR2 60 Reset value TAICLR2 61 Reset value TAOCHR2 62 Reset value TAOCLR2 63 Reset value 140/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 MSB MSB MSB - - - - MSB ...

Page 141

... ST7FOXF1, ST7FOXK1, ST7FOXK2 2 10 bus interface (I 10.5.1 Introduction 2 The I C Bus Interface serves as an interface between the microcontroller and the serial I bus. It provides both multimaster and slave functions, and controls all I sequencing, protocol, arbitration and timing. It supports fast I 10.5.2 Main features Parallel-bus/I Multi-master capability ...

Page 142

... Data register. The SCL frequency (F 2 the I C bus mode. 142/226 MSB interface may be selected between Standard (up to 100 kHz) and Fast ) is controlled by a programmable clock divider which depends on scl ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 69. ACK 8 9 STOP CONDITION ...

Page 143

... ST7FOXF1, ST7FOXK1, ST7FOXK2 2 When the I C cell is enabled, the SDA and SCL ports must be configured as floating inputs. In this case, the value of the external pull-up resistor used depends on the application. 2 When the I C cell is disabled, the SDA and SCL ports revert to being standard I/O port pins. ...

Page 144

... SCL line low (see When the acknowledge pulse is received the EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set. 144/226 Section 10.5.7. for the bit definitions. Figure 71 Transfer sequencing EV2). Figure 71 Transfer sequencing EV3). ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

Page 145

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Closing slave communication After the last data byte is transferred a Stop Condition is generated by the master. The interface detects this condition and sets: EVF and STOPF bits with an interrupt if the ITE bit is set. Then the interface waits for a read of the SR2 register (see EV4) ...

Page 146

... Stop condition. The interface goes automatically back to slave mode (M/SL bit cleared). Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK bit must be cleared just before reading the second last data byte. 146/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 71 Figure 71 Transfer sequencing EV9). Figure 71 Figure 71 Transfer sequencing EV7) ...

Page 147

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Master transmitter Following the address transmission and after SR1 register has been read, the master sends bytes from the DR register to the SDA line via the internal shift register. The master waits for a read of the SR1 register followed by a write in the DR register, ...

Page 148

... EV1 EV3 EV3 Data1 A EV6 EV7 Data1 A EV6 EV8 EV8 Address A Data1 EV1 S Header A Data1 A r EV1 EV3 Address A EV9 EV6 EV8 S Header A r EV5 EV6 ST7FOXF1, ST7FOXK1, ST7FOXK2 A DataN A ..... EV2 EV2 Data NA N .... . EV3- EV3 Data2 A DataN NA .... . EV7 Data Data2 A .... N . ...

Page 149

... ST7FOXF1, ST7FOXK1, ST7FOXK2 subsequent EV4 is not seen. 6. EV4: EVF=1, STOPF=1, cleared by reading SR2 register. 7. EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. 8. EV6: EVF=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). 9. EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register. ...

Page 150

... This bit is set and cleared by software also cleared by hardware when the interface is disabled (PE=0 acknowledge returned 1: Acknowledge returned after an address byte or a data byte is received 150/226 PE ENGC START Read / Write 2 C standard, when GCAL addressing is enabled ST7FOXF1, ST7FOXK1, ST7FOXK2 ACK STOP 2 C slave can 0 ITE ...

Page 151

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 1 = STOP Generation of a Stop condition bit This bit is set and cleared by software also cleared by hardware in master mode. Note: This bit is not cleared when the interface is disabled (PE=0). In master mode stop generation 1: Stop generation after the current byte transfer or after the current Start condition is sent ...

Page 152

... This bit is set by hardware on detection of a Start condition and cleared by hardware on detection of a Stop condition. It indicates a communication in progress on the bus. The BUSY flag of the I2CSR1 register is cleared if a Bus Error occurs communication on the bus 1: Communication ongoing on the bus 152/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 TRA BUSY BTF Read Only 0 ...

Page 153

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 3 = BTF Byte Transfer Finished bit This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt generation if ITE= cleared by software reading SR1 register followed by a read or write of DR register also cleared by hardware when the interface is disabled (PE=0). – ...

Page 154

... An interrupt is generated if ITE= cleared by software reading SR2 register or by hardware when the interface is disabled (PE=0). The SCL line is not held low while BERR= misplaced Start or Stop condition 1: Misplaced Start or Stop condition 154/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 0 AF STOPF Read Only 2 ...

Page 155

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Note Bus Error occurs, a Stop or a repeated Start condition should be generated by the Master to re-synchronize communication, get the transmission acknowledged and the bus released for further communication Bit 0 = GCAL General Call bit (slave mode). This bit is set by hardware when a general call address is detected on the bus while ENGC=1 ...

Page 156

... Read / Write 2 C specified delays select the value corresponding to the . CPU 2 C delay times f CPU < 6 MHz MHz 2 C bus address of the interface (10-bit mode ST7FOXF1, ST7FOXK1, ST7FOXK2 ADD3 ADD2 ADD1 2 C bus address of the 0 ADD9 ADD8 FR1 FR0 ...

Page 157

... ST7FOXF1, ST7FOXK1, ST7FOXK2 2 Table 49 register mapping and reset values Address Register label (Hex.) I2CCR 0064h Reset Value I2CSR1 0065h Reset Value I2CSR2 0066h Reset Value I2CCCR 0067h Reset Value I2COAR1 0068h Reset Value I2COAR2 0069h Reset Value I2CDR 006Ah Reset Value ...

Page 158

... SS: Slave select: This input signal acts as a ‘chip select’ to let the SPI master communicate with slaves individually and to avoid contention on the data lines. Slave SS inputs can be driven by standard I/O ports on the master Device. 158/226 /4 max.) CPU shows the serial peripheral interface (SPI) block diagram. There are ST7FOXF1, ST7FOXK1, ST7FOXK2 ...

Page 159

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 73. Serial peripheral interface block diagram SPIDR Read Buffer MOSI MISO 8-Bit Shift Register SOD bit SCK SS 10.6.4 Functional description A basic example of interconnections between a single master and a single slave is illustrated in Figure The MOSI pins are connected together and the MISO pins are connected together. In this way data is transferred serially between master and slave (most significant bit first) ...

Page 160

... Collision error will occur when the slave writes to the shift register (see collision error 160/226 LSBit MISO MOSI SCK SS +5V Figure 76). (WCOL)). ST7FOXF1, ST7FOXK1, ST7FOXK2 SLAVE MSBit MISO 8-BIT SHIFT REGISTER MOSI SCK SS Not used managed by software Figure , or made free for standard I/O by ...

Page 161

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 75. Generic SS timing diagram MOSI/MISO Master SS Slave SS (if CPHA = 0) Slave SS (if CPHA = 1) Figure 76. Hardware/software slave select management Master mode operation In master mode, the serial clock is output on the SCK pin. The clock frequency, polarity and phase are configured by software (refer to the description of the SPICSR register). ...

Page 162

... An access to the SPICSR register while the SPIF bit is set 2. A write or a read to the SPIDR register Note: While the SPIF bit is set, all writes to the SPIDR register are inhibited until the SPICSR register is read. 162/226 77). Section : Slave select management ST7FOXF1, ST7FOXK1, ST7FOXK2 and ...

Page 163

... ST7FOXF1, ST7FOXK1, ST7FOXK2 The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an Overrun condition (see condition (OVR)). 10.6.5 Clock phase and clock polarity Four possible timing relationships may be chosen by software, using the CPOL and CPHA ...

Page 164

... Clearing the MODF bit is done through a software sequence: 164/226 CPHA = 1 Bit 4 Bit3 Bit 6 Bit 5 Bit 4 Bit3 Bit 6 Bit 5 CPHA = 0 Bit 4 Bit3 Bit 6 Bit 5 Bit 4 Bit3 Bit 6 Bit 5 ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit Bit 2 Bit 1 LSBit ...

Page 165

... ST7FOXF1, ST7FOXK1, ST7FOXK2 1. A read access to the SPICSR register while the MODF bit is set write to the SPICR register. Note: To avoid any conflicts in an application with multiple slaves, the SS pin must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits may be restored to their original state during or after this clearing sequence ...

Page 166

... The multimaster system is principally handled by the MSTR bit in the SPICR register and the MODF bit in the SPICSR register. 166/226 RESULT SPIF = 0 WCOL = 0 Read SPICSR RESULT Read SPIDR WCOL = 0 Figure 79). ST7FOXF1, ST7FOXK1, ST7FOXK2 Note: Writing to the SPIDR register instead of reading it does not reset the WCOL bit ...

Page 167

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 79. Single master / multiple slave configuration SCK MOSI MOSI SCK 5V SS 10.6.7 Low power modes Table 50. Low power mode descriptions Mode WAIT HALT 10.6.8 Interrupts Table 51. Interrupt events Interrupt event SPI End of Transfer Event Master Mode Fault Event Overrun Error Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter) ...

Page 168

... If CPOL is changed at the communication byte boundaries, the SPI must be disabled by resetting the SPE bit. 168/226 SPR2 MSTR CPOL Read / Write Section : Master mode fault (MODF)). The SPE bit is cleared by Table 52: SPI Master mode SCK Section : Master mode fault (MODF)). ST7FOXF1, ST7FOXK1, ST7FOXK2 CPHA SPR1 SPR0 Frequency. 0 ...

Page 169

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 2 = CPHA Clock phase. This bit is set and cleared by software. 0: The first clock transition is the first data capture edge. 1: The second clock transition is the first capture edge. The slave must have the same CPOL and CPHA settings as the master. ...

Page 170

... This bit is set and cleared by software. When set, it disables the alternate function of the SPI output (MOSI in master mode / MISO in slave mode) 0: SPI output enabled (if SPE = 1) 1: SPI output disabled 170/226 ST7FOXF1, ST7FOXK1, ST7FOXK2 OVR MODF - Read / Write (some bits Read only) ...

Page 171

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Bit 1 = SSM SS Management. This bit is set and cleared by software. When set, it disables the alternate function of the SPI SS pin and uses the SSI bit value instead. See Section Slave select management. 0: Hardware management (SS managed by external pin) 1: Software management (internal SS signal controlled by SSI bit. External SS pin free for general-purpose I/O) Bit 0 = SSI SS Internal Mode ...

Page 172

... SPICR 71 Reset Value SPICSR 72 Reset Value 172/226 MSB SPIE SPE SPR2 MSTR SPIF WCOL OVR MODF ST7FOXF1, ST7FOXK1, ST7FOXK2 CPOL CPHA SPR1 SOD SSM LSB x SPR0 x SSI 0 ...

Page 173

... ST7FOXF1, ST7FOXK1, ST7FOXK2 10.7 10-bit A/D converter (ADC) 10.7.1 Introduction The on-chip Analog to Digital Converter (ADC) peripheral is a 10-bit, successive approximation converter with internal sample and hold circuitry. This peripheral has multiplexed analog input channels (refer to device pin out description) that allow the peripheral to convert the analog voltage levels from different sources ...

Page 174

... R ADC ANALOG MUX ADCDRH D9 D8 ADCDRL ) is greater than V (high-level voltage reference) then the AIN DDA ) is lower than V (low-level voltage reference) then the AIN SSA ST7FOXF1, ST7FOXK1, ST7FOXK2 1 f ADC 0 bit ADCCSR CH1 CH0 HOLD CONTROL ANALOG TO DIGITAL CONVERTER C ADC ...

Page 175

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Configuring the A/D conversion The analog input ports must be configured as input, no pull-up, no interrupt (see I/O ports). Using these pins as analog inputs does not affect the ability of the port to be read as a logic input. To assign the analog channel to convert, select the CH[2:0] bits in the ADCCSR register. ...

Page 176

... The number of channels is device dependent. Refer to the device pinout description. 176/226 ADON 0 Read/write (1) CH3 AIN0 0 AIN1 0 AIN2 0 AIN3 0 AIN4 0 AIN5 0 AIN6 0 AIN7 0 AIN8 1 AIN9 1 ST7FOXF1, ST7FOXK1, ST7FOXK2 CH3 CH2 CH1 CH2 CH1 ...

Page 177

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Data register High (ADCDRH) Reset value: xxxx xxxx (xxh Bits 7:0 = D[9:2] MSB of Analog Converted Value ADC Control/data register Low (ADCDRL) Reset value: 0000 00xx (0xh Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = SLOW Slow mode bit This bit is set and cleared by software used together with the SPEED bit in the ADCCSR register to configure the ADC clock speed as shown on the table below ...

Page 178

... A,#$55 ld A,$10 00..FF ld A,$1000 0000..FFFF ld A,(X) 00..FF ld A,($10,X) 00..1FE ld A,($1000,X) 0000..FFFF ld A,[$10] 00..FF ld A,[$10.w] 0000..FFFF ld A,([$10],X) 00..1FE ST7FOXF1, ST7FOXK1, ST7FOXK2 Example nop ld A,#$55 ld A,$55 ld A,($55,X) ld A,([$55],X) jrne loop bset byte,#5 Pointer Pointer Length address size (bytes ...

Page 179

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 59. ST7 addressing mode overview (continued) Mode Long Indirect Indexed Relative Direct Relative Indirect Bit Direct Bit Indirect Bit Direct Relative Bit Indirect Relative 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction following JRxx. ...

Page 180

... The offset is a byte, thus requires only 1 byte after the opcode and allows 00 - 1FE addressing space. 180/226 Instruction MUL SWAP LD CP BCP ST7FOXF1, ST7FOXK1, ST7FOXK2 Function Byte multiplication Shift and rotate operations Swap nibbles Function Load Compare Bit compare Logical operations ...

Page 181

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Indexed mode (long) The offset is a word, thus allowing 64 Kbyte addressing space and requires 2 bytes after the opcode. 11.1.5 Indirect modes (short, long) The required data byte to do the operation is found by its memory address, located in memory (pointer). The pointer address follows the opcode. The indirect addressing mode consists of two ...

Page 182

... CLR INC, DEC TNZ CPL, NEG BSET, BRES BTJT, BTJF SWAP CALL, JP JRxx CALLR ST7FOXF1, ST7FOXK1, ST7FOXK2 Function Clear Increment/decrement Test negative or zero complement Bit operations Bit test and jump operations Shift and rotate operations Swap nibbles Call or jump subroutine ...

Page 183

... ST7FOXF1, ST7FOXK1, ST7FOXK2 11.2 Instruction groups The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Table 64. ST7 instruction set Load and Transfer Stack operation Increment/decrement Compare and tests Logical operations ...

Page 184

... Byte btjf Byte, #3, Jmp1 M btjt Byte, #3, Jmp1 M reg, M tst(Reg - M) reg A = FFH-A reg, M dec Y reg, M Pop CC inc X reg [TBL.w] jrf * ST7FOXF1, ST7FOXK1, ST7FOXK2 Src ...

Page 185

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 65. Illegal opcode detection (continued) Mnemo Description JRPL Jump (plus) JREQ Jump (equal) JRNE Jump (not equal) JRC Jump JRNC Jump JRULT Jump JRUGE Jump JRUGT Jump JRULE Jump ...

Page 186

... Instruction set Table 65. Illegal opcode detection (continued) Mnemo Description WFI Wait for Interrupt XOR Exclusive OR 186/226 Function/Example Dst XOR M A ST7FOXF1, ST7FOXK1, ST7FOXK2 Src ...

Page 187

... ST7FOXF1, ST7FOXK1, ST7FOXK2 12 Electrical characteristics 12.1 Parameter conditions Unless otherwise specified, all voltages are referred to V 12.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at T the selected temperature range) ...

Page 188

... Electrostatic discharge voltage (Human Body model) Electrostatic discharge voltage (Charge Device model according to their reset configuration. SS >V while a negative injection is induced ST7FOXF1, ST7FOXK1, ST7FOXK2 ST7 PIN Maximum value 7.0 (1)( see Section 12.8.3 on page 203 could damage the device if an unintentional SS maximum is respected ...

Page 189

... ST7FOXF1, ST7FOXK1, ST7FOXK2 Table 67. Current characteristics Symbol I VDD I VSS I IO (2)(3) I INJ(PIN) ΣI (2) INJ(PIN) 1. All power (V ) and ground ( must never be exceeded. This is implicitly insured if V INJ(PIN) cannot be respected, the injection current must be limited externally to the I injection is induced by V pads, there is no positive injection current, and the corresponding V 3 ...

Page 190

... DD slope is outside these values, the LVD may not release properly the DD down ensure optimum restart conditions. Refer to DD Figure 89 on page 207. ST7FOXF1, ST7FOXK1, ST7FOXK2 Conditions Min = 8 MHz max. 4.5 ≤5 ...

Page 191

... ST7FOXF1, ST7FOXK1, ST7FOXK2 12.3.3 Internal RC oscillator To improve clock stability and frequency accuracy recommended to place a decoupling capacitor, typically 100 nF, between the V device Internal RC oscillator calibrated at 5.0 V The ST7 internal clock can be supplied by an internal RC oscillator (selectable by option byte). Table 71. Internal RC oscillator characteristics (5.0 V calibration) ...

Page 192

... All I/O pins in input mode with a static value at V OSC based on f divided by 32. All I/O pins in input mode with a static value at V OSC or V (no load). Data tested in production (no load), LVD disabled. Data based on characterization results, SS max. CPU ST7FOXF1, ST7FOXK1, ST7FOXK2 Typ Max = 4 MHz 2.5 4 MHz 5 MHz 1 MHz 2 ...

Page 193

... ST7FOXF1, ST7FOXK1, ST7FOXK2 12.4.2 On-chip peripherals Table 73. On-chip peripheral characteristics Symbol I DD(SPI) I 12-bit Auto-Reload timer supply current DD(AT) I DD(I2C) I ADC supply current when converting DD(ADC) 1. Data based on a differential I communication (data sent equal to 55h). 2. Data based on a differential I running in PWM mode Data based on a differential I ...

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... MHz to 8 MHz, CPU (1)(2)(3) C interface) I2CCCR Value = =4.7kΩ 84h 11h 25h 62h speed. SCL ST7FOXF1, ST7FOXK1, ST7FOXK2 , and T unless otherwise specified. OSC A Min = 4.5 to 5.5 V Table 75 MHz CPU DD R =3.3kΩ 84h 86h 8Ah 25h ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 12.5.2 SPI interface Subject to general operating conditions for V Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SS, SCK, MOSI, MISO). Table 76. SPI interface characteristics Symbol f SCK SPI clock frequency 1/t c(SCK) t r(SCK) SPI clock rise and fall time ...

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... MSB OUT BIT6 OUT t t su(SI) h(SI) MSB su(SS) c(SCK) t w(SCKH) t a(SO w(SCKL) v(SO) MSB OUT su(SI) h(SI) MSB IN DD ST7FOXF1, ST7FOXK1, ST7FOXK2 t h(SS) t h(SO) t r(SCK) t f(SCK) LSB OUT LSB IN BIT1 IN and 0.7xV DD t h(SS) t h(SO) t r(SCK) t f(SCK) BIT6 OUT LSB OUT BIT1 IN LSB IN and 0.7xV DD ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 Figure 85. SPI master timing diagram SS INPUT CPHA = 0 CPOL = 0 CPHA = 0 CPOL = 1 CPHA = 1 CPOL = 0 CPHA = 1 CPOL = 1 MISO INPUT MOSI See note 2 OUTPUT 1. Measurement points are done at CMOS levels: 0.3xV 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released ...

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... OSC1/CLKIN high or low (1) time (1) OSC1/CLKIN rise or fall time OSCx/CLKIN Input leakage current 90% 10 f(OSC1 or CLKIN) r(OSC1 or CLKIN)) OSC2 OSC1/CLKIN (1) Conditions Frequency time ST7FOXF1, ST7FOXK1, ST7FOXK2 Conditions Min Typ 0.7xV DD V 0.3xV SS see Figure 86 15 ≤V ≤ ...

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... ST7FOXF1, ST7FOXK1, ST7FOXK2 12.6.2 Crystal and ceramic resonator oscillators The ST7 internal clock can be supplied with ten different Crystal/Ceramic resonator oscillators. All the information given in this paragraph are based on characterization results with specified typical external components. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and start-up stabilization time ...

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... Write/Erase Section 12.3.1 on =−40 to +85 °C T (1) A bytes (2) Data retention T Write erase cycles Read / Write / Erase f CPU (4) Supply current No Read/No Write Power down mode / decreases. A ST7FOXF1, ST7FOXK1, ST7FOXK2 Min Typ 1.6 Conditions Min Typ with 4.5 page 190 5 =+25 °C T 0.64 A =+55 °C ( =+25 ° ...