ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 128

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

On-chip peripherals
128/226
Figure 65. One pulse mode sequence
When a valid event occurs on the ICAP1 pin, the counter value is loaded in the ICR1
register. The counter is then initialized to FFFCh, the OLVL2 bit is output on the OCMP1 pin
and the ICF1 bit is set.
Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the
ICIE bit is set.
Clearing the input capture interrupt request (that is, clearing the ICFi bit) is done in two
steps:
1.
2.
The OC1R register value required for a specific timing application can be calculated using
the following formula:
Equation 3
Where:
t =
f
PRESC
If the timer clock is an external clock the formula is:
Equation 4
Where:
t =
f
When the value of the counter is equal to the value of the contents of the OC1R register, the
OLVL1 bit is output on the OCMP1 pin, (see
CPU
EXT
Reading the SR register while the ICFi bit is set.
Accessing (reading or writing) the ICiLR register.
=
=
=
OCiR =
pulse period (in seconds)
CPU clock frequency (in hertz)
timer prescaler factor (2, 4 or 8 depending on the CC[1:0] bits, see
Control register 2 (TACR2) on page
pulse period (in seconds)
external timer clock frequency (in hertz)
t
*
f
EXT
-5
When event
occurs on
OCiR value =
= OC1R
ICAP1
counter
When
Figure
One pulse mode cycle
PRESC
t
OCMP1 = OLVL1
OCMP1 = OLVL2
Counter is reset
134)
*
ICR1 = counter
ICF1 bit is set
f
CPU
to FFFCh
66).
ST7FOXF1, ST7FOXK1, ST7FOXK2
- 5
: Timer A