ST7FOXK1 STMicroelectronics, ST7FOXK1 Datasheet - Page 150

• Manufacturer Part Number: ST7FOXK1
• Description: Low cost flash 8bit micro
• Manufacturer: STMicroelectronics

Specifications of ST7FOXK1

• 4 To 8 Kbytes Single Voltage Extended Flash (xflash) Program Memory With Read-out Protection In-circuit Programming And In-application Programming (icp And Iap) Endurance: 1K write/erase cycles guaranteed Data retention
• Clock Sources: Internal trimmable 8 MHz RC oscillator, auto wakeup internal low power - low frequency oscillator, crystal/ceramic resonator or external clock
• Five Power Saving Modes: Halt, Active-Halt, Auto Wakeup from Halt, Wait and Slow
• A/d Converter: up to 10 input channels

On-chip peripherals
10.5.7
Note:
Note:
150/226
Register description
I
Reset value: 0000 0000 (00h)
Bits 7:6 = Reserved. Forced to 0 by hardware.
Bit 5 = PE Peripheral Enable bit
When PE=0, all the bits of the CR register and the SR register except the Stop bit are reset.
All outputs are released while PE=0
When PE=1, the corresponding I/O pins are selected by hardware as alternate functions.
To enable the I
activates the interface (only PE is set).
Bit 4 = ENGC Enable General Call bit
In accordance with the I
only receive data. It will not transmit data to the master.
Bit 3 = START Generation of a Start condition bit. This bit is set and cleared by software. It
is also cleared by hardware when the interface is disabled (PE=0) or when the Start
condition is sent (with interrupt generation if ITE=1).
Bit 2 = ACK Acknowledge enable bit
2
C Control register (I2CCR)
This bit is set and cleared by software.
0: Peripheral disabled
1: Master/Slave capability
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0). The 00h General Call address is acknowledged (01h ignored).
0: General Call disabled
1: General Call enabled
In master mode:
0: No start generation
1: Repeated start generation
In slave mode:
0: No start generation
1: Start generation when the bus is free
This bit is set and cleared by software. It is also cleared by hardware when the interface
is disabled (PE=0).
0: No acknowledge returned
1: Acknowledge returned after an address byte or a data byte is received
7
0
2
C interface, write the CR register TWICE with PE=1 as the first write only
0
2
C standard, when GCAL addressing is enabled, an I
PE
ENGC
Read / Write
START
ST7FOXF1, ST7FOXK1, ST7FOXK2
ACK
STOP
2
C slave can
ITE
0